Lot of people use SDRAM with FPGAs. http://www.google.com/search?channel=fs&q=fpga+sdram&ie=utf-8&oe=utf-8 http://www.google.com/search?channel=fs&q=fpga+sdram&

Lot of people use SDRAM with FPGAs. http://www.google.com/search?channel=fs&q=fpga+sdram&ie=utf-8&oe=utf-8 http://www.google.com/search?channel=fs&q=fpga+sdram&#38... SDRAM is used commonly with FPGAs for storing largish amounts of data at a reasonable price (static RAM is fast, predictable, and very expensive for large fast memory arrays). SDRAMs are horribly complex state machine driven pipelined devices. On a system I was working on, a simple write operation to the SDRAM could vary from several clock cycles to 52 (IIRC) clock cycles, depending on what was going on before the "simple" write. I forgot what the worst case stack up was, but it was probably something about a refresh followed by a page miss that needed a precharge... AnandTech has a good intro... note the simplified state machine diagram (Figure 2) is not simple. If they published the full state machine, your head would explode. http://www.anandtech.com/show/3851/everything-you-always-wanted-to-know-about-sdram-memory-but-were-afraid-to-ask/ http://www.anandtech.com/show/3851/everything-you-always-wan... Trivia: The data throughput listed by SDRAM manufacturers is the best case sequential access fully pipelined scenario when all -nine- eight planets align. Speculating here: The variability of SDRAM access latency is one reason for putting a high speed cache in front of it. For instance, the cache could be a simple FIFO operation to buffer the data to avoid dropping data when an operation got hit by a long latency stackup. The SDRAM may have the average throughput to handle the data stream, but the (unpredictable) major bumps in latency may required "cache" buffering to keep from dropping data.