I understand that it's very possible the FPGA is the problem. However, it's a cakewalk to continuously monitor and calibrate FPGA latencies. In fact, it's pro

I understand that it's very possible the FPGA is the problem. However, it's a cakewalk to continuously monitor and calibrate FPGA latencies. In fact, it's probably done in conjunction with the calibration of APDs/PMTs. If they aren't doing this, then the whole experiment has much bigger problems. My point is that I personally feel it's incredibly wrong to single out the FPGA DAQ systems, as the discrepancy of 60ns is so incredibly large compared to what is easily attainable, and the delay is something that's always compensated for in calibration. I think that there's some other error in the system, and my gut feeling is that it's due either to geometry or calibration.