I'd argue exposing the IEEE 754 binary64 (aka f64; aka double) FMA unit's `((u52 * u52) & (1 << 51)) + u64` and `((u52 * u52) >> 52) + u64` (low half/high half

I'd argue exposing the IEEE 754 binary64 (aka f64; aka double) FMA unit's `((u52 * u52) & (1 << 51)) + u64` and `((u52 * u52) >> 52) + u64` (low half/high half, respectively) in the AVX-512IFMA instruction set was quite effective for the cost being comparatively cheap bypassing of exponent/sign handling and corresponding instruction decoder additions. Note: these help for wide multiply, as needed most prominent by ed25519 and RSA. They do apply for "just" 256bit vectors using 4 lanes of 64bit (where multiplicands are just the low 52bits), without the AVX-512-typical clock penalty. In similar spirit, it would have been nice to get emulated AVX-512 on AMD and Intel's E-cores, as it uses just one instruction to process twice the width, reducing the frontend throughout requirements. Also said AVX-512IFMA is rather nice, regardless of vector width.