4 ms·
Much more limited capability wise, but much tighter guarantees about latency. More like a 80Mhz AVR 8bit than an ARM coprocessor. The real shame of modern micr
by fps-hero 5y ago
Much more limited capability wise, but much tighter guarantees about latency. More like a 80Mhz AVR 8bit than an ARM coprocessor.
The real shame of modern microcontrollers is the decoupling of peripherals and GPIO from the main processor. It prevents these sorts of hacks as all access has to be through the memory bus, effectively capping bitbanging at sub 10MHz speeds.
- guenthert 5y ago> but much tighter guarantees about latency Could you clarify that? It was my understanding that the PRUs of the TI AM355x Sitara specify execution time true to the cycle.
- fps-hero 5y agoBy that I mean how IO is coupled to the processor. In AVR8 (and other older processors I presume) GPIO access was via a CPU register, thus a single instruction (one clock RISC) can directly modify the GPIO state. Every GPIO implementation I’ve seen on modern processors accesses it via a memory mapped peripheral. The difference being accessing a memory bus is not a single cycle operation. You have to wait for the bus to be free, then wait to fetch or write the data. The most extreme analogous example of this is modern cpus are effectively infinitely fast but bounded by cache misses that necessitate memory access. This is fundamentally why every toggle a GPIO pin benchmark is flawed. What is really being measured is memory bus latency. This misunderstanding is why people have trouble reconciling why a multi ghz processor cannot also bitbang GPIO at ghz speeds, although if such a processor existed it would be amazing.
- rasz 5y agoThroughput isnt even the main problem, its the latency that kills you in modern GPIOs.