I worked with FPGAs for my master's thesis (specifically, scheduling workloads for a runtime-reconfigurable FPGA). The bad taste of the proprietary tooling is w

I worked with FPGAs for my master's thesis (specifically, scheduling workloads for a runtime-reconfigurable FPGA). The bad taste of the proprietary tooling is what made me abandon the field. I've always kept an eye on the GHDL and gEDA projects, but open progress has been glacial. The Icestorm project finally opened up FPGAs enough for me to want to work with them, but it came 15 years too late. I agree with you that designing for FPGA hasn't become any easier since the introduction of hardware accelerators inside the chip (multipliers, block rams etc) but the lack of standardization has been hurting the field for more than 20 years. Even upgrading a project from Xilinx $chip to Xilinx $chip++ was a multi-week project.