I think it might be trying to explain the difference between a format for use when building ASICs and one that targets fpga architecture. With an fpga, there is

I think it might be trying to explain the difference between a format for use when building ASICs and one that targets fpga architecture. With an fpga, there is a structure (the tile) that contains some ram some, luts and other blocks. The luts are reconfigurable, and so is the wiring, but otherwise the fpga is mostly fixed. So this is quite different than an asic, where there are more cell types (flip flops, logic gates, or fets, etc) and they can be freely placed in the design.