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SPARC has been open for decades: * https://sparc.org https://sparc.org There have been non-Sun/Oracle CPUs available since the 1990s. Fujitsu sells entire pro

SPARC has been open for decades: * https://sparc.org https://sparc.org There have been non-Sun/Oracle CPUs available since the 1990s. Fujitsu sells entire product lines on them (and there's a Top 500 cluster built around SPARC.) This also included the 'BIOS' (IEEE 1275-1994): * https://en.wikipedia.org/wiki/Open_Firmware https://en.wikipedia.org/wiki/Open_Firmware And accessory bus (IEEE 1496-1993): * https://en.wikipedia.org/wiki/SBus https://en.wikipedia.org/wiki/SBus

audunw 5y ago
I dont think SPARC is a very good ISA. Before RISC-V there was also OpenRISC, which early on had some of the same traction as RISC-V in the open source community. But both SPARC and OpenRISC has branch delay slots, which was, if I remember correctly, one of the things the designers of RISC-V wanted to avoid to have a more scalable ISA. Branch delay slots are supposedly a big issue when designing high end superscalar cores. RISC-V is very well thought out when it comes to scaling from the smaller MCU cores to the largest supercomputer CPUs. With a coming revision the code density with the compressed extension is even better than ARM Thumb, while being better designed than Thumb (no mode switching)
- foxfluff 5y ago
  > With a coming revision the code density with the compressed extension is even better than ARM Thumb I'd love to read about this revision and understand how it achieves that improvement. Do you have a link handy?
  - __s 5y ago
    https://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-107.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-...
  - YorkshireSeason 5y ago
    https://github.com/riscv/riscv-code-size-reduction https://github.com/riscv/riscv-code-size-reduction is the place to check.
hajile 5y ago
Does SPARC still have rotating register windows that are extremely hard to use effectively?

audunw 5y ago

I dont think SPARC is a very good ISA. Before RISC-V there was also OpenRISC, which early on had some of the same traction as RISC-V in the open source community. But both SPARC and OpenRISC has branch delay slots, which was, if I remember correctly, one of the things the designers of RISC-V wanted to avoid to have a more scalable ISA. Branch delay slots are supposedly a big issue when designing high end superscalar cores. RISC-V is very well thought out when it comes to scaling from the smaller MCU cores to the largest supercomputer CPUs. With a coming revision the code density with the compressed extension is even better than ARM Thumb, while being better designed than Thumb (no mode switching)

foxfluff 5y ago
> With a coming revision the code density with the compressed extension is even better than ARM Thumb I'd love to read about this revision and understand how it achieves that improvement. Do you have a link handy?
- __s 5y ago
  https://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-107.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-...
- YorkshireSeason 5y ago
  https://github.com/riscv/riscv-code-size-reduction https://github.com/riscv/riscv-code-size-reduction is the place to check.

hajile 5y ago

Does SPARC still have rotating register windows that are extremely hard to use effectively?