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I honestly done understand they hype around RISC-V, it’s seems like reinventing the wheel. Sure it’s open, but so is OpenPower; and that’s a lot more mature wit

by mnd999 5y ago

I honestly done understand they hype around RISC-V, it’s seems like reinventing the wheel. Sure it’s open, but so is OpenPower; and that’s a lot more mature with better software support. I’m sure it’s not the only one either. Everything new is old I guess. Edit: Tesla lies in their marketing, the industry is sexist, Rust is overhyped, Wayland still isn't very usable. If I'm gonna get downvotes, I might as well go big.

boondaburrah 5y ago
I mean you're right, but OpenPower showed up late to the game, after the RISC-V hype train was already going, almost as if IBM wanted to derail it. (More likely IBM saw RISC-V prove that it was viable and wanted people to be using Power instead. (So not so much derail it as derail it and put me on the rails instead))
- throw0101a 5y ago
  SPARC has been open for decades: * https://sparc.org https://sparc.org There have been non-Sun/Oracle CPUs available since the 1990s. Fujitsu sells entire product lines on them (and there's a Top 500 cluster built around SPARC.) This also included the 'BIOS' (IEEE 1275-1994): * https://en.wikipedia.org/wiki/Open_Firmware https://en.wikipedia.org/wiki/Open_Firmware And accessory bus (IEEE 1496-1993): * https://en.wikipedia.org/wiki/SBus https://en.wikipedia.org/wiki/SBus
  - audunw 5y ago
    I dont think SPARC is a very good ISA. Before RISC-V there was also OpenRISC, which early on had some of the same traction as RISC-V in the open source community. But both SPARC and OpenRISC has branch delay slots, which was, if I remember correctly, one of the things the designers of RISC-V wanted to avoid to have a more scalable ISA. Branch delay slots are supposedly a big issue when designing high end superscalar cores. RISC-V is very well thought out when it comes to scaling from the smaller MCU cores to the largest supercomputer CPUs. With a coming revision the code density with the compressed extension is even better than ARM Thumb, while being better designed than Thumb (no mode switching)
    - foxfluff 5y ago
      > With a coming revision the code density with the compressed extension is even better than ARM Thumb I'd love to read about this revision and understand how it achieves that improvement. Do you have a link handy?
      - __s 5y ago
        https://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-107.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-...
      - YorkshireSeason 5y ago
        https://github.com/riscv/riscv-code-size-reduction https://github.com/riscv/riscv-code-size-reduction is the place to check.
  - hajile 5y ago
    Does SPARC still have rotating register windows that are extremely hard to use effectively?
zozbot234 5y ago
If anything, it's a clean slate design and that makes it way simpler than the legacy ISA's. To the point that a single, easy to target base ISA can be used for anything from bare-metal embedded devices to high-end supercomputers and hyperscale server hardware. That's quite unprecedented.
- goodpoint 5y ago
  Also, it's very simple but cleverly designed to allow cheap and power-efficient CPUs. Vectoring being one of the best features.
goodpoint 5y ago
> Tesla lies in their marketing, the industry is sexist, Rust is overhyped, Wayland still isn't very usable I agree with everything else but RV is actually a big improvement over OpenPower and many other ISAs.
ngcc_hk 5y ago
The chinese want it. The open crowd thought they are in charge. And given the broken patent process when it will be invoked. It will run for awhile before what the reality is biting. Still early stage. But just playing architecture game is hard. You need some reasons like lower power … for it to play.
dkjaudyeqooe 5y ago
You could say that about most open source software. How did that turn out?
panick21_ 5y ago
OpenPower was not 'open'. They were fake open for marketing reasons. You could not simply build an OpenPower chip and sell it. Actually only long after RISC-V both OpenPower and MIPS opened up more. The only thing that was actually open was SPARCv8 and that had a number of limitations that the creates of RISC-V didn't want. And Oracle had closed it up again after that. OpenRISC was more a chip, not really an ISA design. And it wasn't 64 Bit when RISC-V started either. And RISC-V also does a number of new things and removes some other things. All of this has been extensively written about by the creators of RISC-V, you could just go read it.

by mnd999 5y ago

boondaburrah 5y ago

I mean you're right, but OpenPower showed up late to the game, after the RISC-V hype train was already going, almost as if IBM wanted to derail it. (More likely IBM saw RISC-V prove that it was viable and wanted people to be using Power instead. (So not so much derail it as derail it and put me on the rails instead))

throw0101a 5y ago
SPARC has been open for decades: * https://sparc.org https://sparc.org There have been non-Sun/Oracle CPUs available since the 1990s. Fujitsu sells entire product lines on them (and there's a Top 500 cluster built around SPARC.) This also included the 'BIOS' (IEEE 1275-1994): * https://en.wikipedia.org/wiki/Open_Firmware https://en.wikipedia.org/wiki/Open_Firmware And accessory bus (IEEE 1496-1993): * https://en.wikipedia.org/wiki/SBus https://en.wikipedia.org/wiki/SBus
- audunw 5y ago
  I dont think SPARC is a very good ISA. Before RISC-V there was also OpenRISC, which early on had some of the same traction as RISC-V in the open source community. But both SPARC and OpenRISC has branch delay slots, which was, if I remember correctly, one of the things the designers of RISC-V wanted to avoid to have a more scalable ISA. Branch delay slots are supposedly a big issue when designing high end superscalar cores. RISC-V is very well thought out when it comes to scaling from the smaller MCU cores to the largest supercomputer CPUs. With a coming revision the code density with the compressed extension is even better than ARM Thumb, while being better designed than Thumb (no mode switching)
  - foxfluff 5y ago
    > With a coming revision the code density with the compressed extension is even better than ARM Thumb I'd love to read about this revision and understand how it achieves that improvement. Do you have a link handy?
    - __s 5y ago
      https://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-107.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-...
    - YorkshireSeason 5y ago
      https://github.com/riscv/riscv-code-size-reduction https://github.com/riscv/riscv-code-size-reduction is the place to check.
- hajile 5y ago
  Does SPARC still have rotating register windows that are extremely hard to use effectively?

zozbot234 5y ago

If anything, it's a clean slate design and that makes it way simpler than the legacy ISA's. To the point that a single, easy to target base ISA can be used for anything from bare-metal embedded devices to high-end supercomputers and hyperscale server hardware. That's quite unprecedented.

goodpoint 5y ago
Also, it's very simple but cleverly designed to allow cheap and power-efficient CPUs. Vectoring being one of the best features.

goodpoint 5y ago

> Tesla lies in their marketing, the industry is sexist, Rust is overhyped, Wayland still isn't very usable I agree with everything else but RV is actually a big improvement over OpenPower and many other ISAs.

ngcc_hk 5y ago

The chinese want it. The open crowd thought they are in charge. And given the broken patent process when it will be invoked. It will run for awhile before what the reality is biting. Still early stage. But just playing architecture game is hard. You need some reasons like lower power … for it to play.

dkjaudyeqooe 5y ago

You could say that about most open source software. How did that turn out?

panick21_ 5y ago

OpenPower was not 'open'. They were fake open for marketing reasons. You could not simply build an OpenPower chip and sell it. Actually only long after RISC-V both OpenPower and MIPS opened up more. The only thing that was actually open was SPARCv8 and that had a number of limitations that the creates of RISC-V didn't want. And Oracle had closed it up again after that. OpenRISC was more a chip, not really an ISA design. And it wasn't 64 Bit when RISC-V started either. And RISC-V also does a number of new things and removes some other things. All of this has been extensively written about by the creators of RISC-V, you could just go read it.