I don't think it's the same. That proposal seems to be be an intermediate format that VHDL and Verilog (and things like MyHDL/SpinalHDL). The FPGA Interchange F

I don't think it's the same. That proposal seems to be be an intermediate format that VHDL and Verilog (and things like MyHDL/SpinalHDL). The FPGA Interchange Format seems to tackle a more compelling challenge: A format for defining the routed (or maybe partially-routed) design (actually, it seems like a general-purpose netlist that can describe the FPGA before and also after place & route).