5 ms·
There is a nice discussion[1] about the same in SymbiFlow[2]. I hope, they at least read through it. [1] https://github.com/SymbiFlow/ideas/issues/19 https://g
by xvilka 5y ago
There is a nice discussion[1] about the same in SymbiFlow[2]. I hope, they at least read through it.
[1] https://github.com/SymbiFlow/ideas/issues/19 https://github.com/SymbiFlow/ideas/issues/19
[2] https://symbiflow.github.io/ https://symbiflow.github.io/
- phendrenad2 5y agoI don't think it's the same. That proposal seems to be be an intermediate format that VHDL and Verilog (and things like MyHDL/SpinalHDL). The FPGA Interchange Format seems to tackle a more compelling challenge: A format for defining the routed (or maybe partially-routed) design (actually, it seems like a general-purpose netlist that can describe the FPGA before and also after place & route).