we've commonly used verilog (just instantiating gates) to do this - partly because for a period (ie the 90s) we didn't really trust synthesis tools to get it ri

we've commonly used verilog (just instantiating gates) to do this - partly because for a period (ie the 90s) we didn't really trust synthesis tools to get it right and always ran gatesim before we taped out just in case. My crowning glory hack from that era was a perl script that read verilog netlists and lisp placement data between the place and route stages of the P&R tool and did location dependent scan insertion producing a netlist and a the lisp instructions to the P&R tool to fix it up