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HDLs like VHDL and Verilog are at a different level. If HDLs are like C, the interchange format is more comparable to a .o file. That being said, EDIF already

HDLs like VHDL and Verilog are at a different level. If HDLs are like C, the interchange format is more comparable to a .o file. That being said, EDIF already exists.

Taniwha 5y ago
we've commonly used verilog (just instantiating gates) to do this - partly because for a period (ie the 90s) we didn't really trust synthesis tools to get it right and always ran gatesim before we taped out just in case. My crowning glory hack from that era was a perl script that read verilog netlists and lisp placement data between the place and route stages of the P&R tool and did location dependent scan insertion producing a netlist and a the lisp instructions to the P&R tool to fix it up
Rochus 5y ago
You can pretty well represent low-level netlists in Verilog. EDIF is big and complex and there are different only partially compatible versions in parallel use.
mithro 5y ago
On a semi-related note, Google has also been investigating in improving support for SystemVerilog support in open source tooling -> https://opensource.googleblog.com/2021/09/open-source-systemverilog-tools-in-asic-design.html https://opensource.googleblog.com/2021/09/open-source-system...
ip26 5y ago
HDL can really be either. I would compare RTL to assembly, and gate netlists to .o files.