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The problem is not that you need a unifying language to do this , you already have 2 vhdl and verilog which are mature etc. The problem is and has always been v
by xphos 5y ago
The problem is not that you need a unifying language to do this , you already have 2 vhdl and verilog which are mature etc. The problem is and has always been vendors don't want to release their tools. It's like saying only one assembly language should exist. Why? There can be multiple versions of assembly but the vendors of these things need to release a version of llvm or gcc that allows people to build for there devices without having to pay 10000s of dollars to use them.
Players like Xilinx have held out their compliers and instead selling them and using lawsuit to prevent people from reverse engineering there IP. This hasn't stopped people or lesser players like lattice from doing this but it's definitely slowed it down. I think open sourcing or releasing the compliers is just kind of forced because what new company would but a complier if they can get one for free (yosys).
- duskwuff 5y agoHDLs like VHDL and Verilog are at a different level. If HDLs are like C, the interchange format is more comparable to a .o file. That being said, EDIF already exists.
- Taniwha 5y agowe've commonly used verilog (just instantiating gates) to do this - partly because for a period (ie the 90s) we didn't really trust synthesis tools to get it right and always ran gatesim before we taped out just in case. My crowning glory hack from that era was a perl script that read verilog netlists and lisp placement data between the place and route stages of the P&R tool and did location dependent scan insertion producing a netlist and a the lisp instructions to the P&R tool to fix it up
- Rochus 5y agoYou can pretty well represent low-level netlists in Verilog. EDIF is big and complex and there are different only partially compatible versions in parallel use.
- mithro 5y agoOn a semi-related note, Google has also been investigating in improving support for SystemVerilog support in open source tooling -> https://opensource.googleblog.com/2021/09/open-source-systemverilog-tools-in-asic-design.html https://opensource.googleblog.com/2021/09/open-source-system...
- ip26 5y agoHDL can really be either. I would compare RTL to assembly, and gate netlists to .o files.
- octoberfranklin 5y agoXilinx is a software company. They consider their chips to be the copy-protection dongles for the software. It's nuts, and it infuriates me, but looking at it this way explains a whole lot of their behavior.