Edit: Oops, leaving this for posterity, but there's an error below. At the point marked OOPS cmpxchg or another atomic op is the (only?) way to avoid a race con

Edit: Oops, leaving this for posterity, but there's an error below. At the point marked OOPS cmpxchg or another atomic op is the (only?) way to avoid a race condition when there's a potential interrupt between the write-back instruction of the atomic operation and the comparison to the generation. My bad. -- For this use case, I don't think the approach I mentioned requires an atomic cmpxchg. Fast path (no pre-emption): - Read generation number shared memory location (GNSML) to register - Perform atomic operation - Compare (non-atomic) *GNSML to register [OOPS] - Equal, so continue Slow path (pre-emption): - Read generation number shared memory location (GNSML) to register - Perform (part of) atomic operation -- Pre-emption occurs -- kernel updates GNSML, already has plenty of memory barriers with mode transitions - Perform (rest of) atomic operation - Compare (non-atomic) *GNSML to register -- because we're reading on the far side of the barrier, see new value - Different, so jump to restart