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> and some lattice chips Lattice has been by far the favorite of the FOSS community, but there's been more news: - https://github.com/YosysHQ/apicula https://
by floatboth 5y ago
> and some lattice chips
Lattice has been by far the favorite of the FOSS community, but there's been more news:
- https://github.com/YosysHQ/apicula https://github.com/YosysHQ/apicula has appeared for Gowin FPGAs found on e.g. Sipeed Tang Nano boards (very cheap on AliExpress)
- a vendor called QuickLogic made SoCs that only use the FOSS toolchain for the FPGA part, out of the box: https://www.quicklogic.com/products/soc/eos-s3-microcontroller/ https://www.quicklogic.com/products/soc/eos-s3-microcontroll...
- throwmeawaysoon 5y ago>Lattice has been by far the favorite of the FOSS community i'm interested in the OSS flows but i haven't dug in yet. so some questions (if you have experience): isn't it only for their ice40 chips? and how smooth is the flow from RTL to bitstream to deploy? one hesitation i have with jumping in is that i'm working on accelerator type stuff, so my designs typically need on the other of 30k-50k LUTs. will yosys+nextpnr let me deploy such a design to some chip?
- floatboth 5y agoI don't have that much experience (don't really have many use cases for FPGAs personally tbh) but: Icestorm is for iCE40, Trellis is for ECP5 (which comes in variants up to 85k LUTs); the flow is simple enough to do manually but there are things that make it one-click. This tutorial series https://youtube.com/playlist?list=PLEBQazB0HUyT1WmMONxRZn9NmQ_9CIKhb https://youtube.com/playlist?list=PLEBQazB0HUyT1WmMONxRZn9Nm... uses one. As for handling really big designs, I don't know.