4 ms·

What’s wrong with current state except that the chips have lead time of 52+ weeks?

by lnsru 5y ago

colejohnson66 5y ago
The development side. Compiling and simulating your Verilog/VHDL can be done with open source software, but to put it on the FPGA itself, you generally need closed source (and sometimes paid) tools to generate the bitstreams. Contrast that with microcontrollers such as the ATMega which can be programmed from start to finish using an entirely FOSS stack - even the bootloader and programmer. And for some reason, these companies consider the bitstream formats trade secrets and refuse to document them at all.
- throwmeawaysoon 5y ago
  this is true in general but 1) vivado webpack edition (ie free) lets you write (and flash) a bitstream for some of the small chips. i know it at least works for the artix-7 family because i'm doing it every day lately 2) for the artix-7 (and some lattice chips) you supposedly can use OSS (https://github.com/SymbiFlow/prjxray https://github.com/SymbiFlow/prjxray). i haven't tried it yet but one problem i can foresee is that the OSS tools won't infer stuff like brams and dsp. in fact the symbiflow people (i think?) explicitly call this out as the part of the project that's a work in progress. some useful links: https://arxiv.org/abs/1903.10407 https://arxiv.org/abs/1903.10407 https://github.com/YosysHQ/nextpnr https://github.com/YosysHQ/nextpnr https://www.rapidwright.io/ https://www.rapidwright.io/
  - floatboth 5y ago
    > and some lattice chips Lattice has been by far the favorite of the FOSS community, but there's been more news: - https://github.com/YosysHQ/apicula https://github.com/YosysHQ/apicula has appeared for Gowin FPGAs found on e.g. Sipeed Tang Nano boards (very cheap on AliExpress) - a vendor called QuickLogic made SoCs that only use the FOSS toolchain for the FPGA part, out of the box: https://www.quicklogic.com/products/soc/eos-s3-microcontroller/ https://www.quicklogic.com/products/soc/eos-s3-microcontroll...
    - throwmeawaysoon 5y ago
      >Lattice has been by far the favorite of the FOSS community i'm interested in the OSS flows but i haven't dug in yet. so some questions (if you have experience): isn't it only for their ice40 chips? and how smooth is the flow from RTL to bitstream to deploy? one hesitation i have with jumping in is that i'm working on accelerator type stuff, so my designs typically need on the other of 30k-50k LUTs. will yosys+nextpnr let me deploy such a design to some chip?
      - floatboth 5y ago
        I don't have that much experience (don't really have many use cases for FPGAs personally tbh) but: Icestorm is for iCE40, Trellis is for ECP5 (which comes in variants up to 85k LUTs); the flow is simple enough to do manually but there are things that make it one-click. This tutorial series https://youtube.com/playlist?list=PLEBQazB0HUyT1WmMONxRZn9NmQ_9CIKhb https://youtube.com/playlist?list=PLEBQazB0HUyT1WmMONxRZn9Nm... uses one. As for handling really big designs, I don't know.

What’s wrong with current state except that the chips have lead time of 52+ weeks?

by lnsru 5y ago

What’s wrong with current state except that the chips have lead time of 52+ weeks?

The development side. Compiling and simulating your Verilog/VHDL can be done with open source software, but to put it on the FPGA itself, you generally need closed source (and sometimes paid) tools to generate the bitstreams. Contrast that with microcontrollers such as the ATMega which can be programmed from start to finish using an entirely FOSS stack - even the bootloader and programmer. And for some reason, these companies consider the bitstream formats trade secrets and refuse to document them at all.

throwmeawaysoon 5y ago
this is true in general but 1) vivado webpack edition (ie free) lets you write (and flash) a bitstream for some of the small chips. i know it at least works for the artix-7 family because i'm doing it every day lately 2) for the artix-7 (and some lattice chips) you supposedly can use OSS (https://github.com/SymbiFlow/prjxray https://github.com/SymbiFlow/prjxray). i haven't tried it yet but one problem i can foresee is that the OSS tools won't infer stuff like brams and dsp. in fact the symbiflow people (i think?) explicitly call this out as the part of the project that's a work in progress. some useful links: https://arxiv.org/abs/1903.10407 https://arxiv.org/abs/1903.10407 https://github.com/YosysHQ/nextpnr https://github.com/YosysHQ/nextpnr https://www.rapidwright.io/ https://www.rapidwright.io/
- floatboth 5y ago
  > and some lattice chips Lattice has been by far the favorite of the FOSS community, but there's been more news: - https://github.com/YosysHQ/apicula https://github.com/YosysHQ/apicula has appeared for Gowin FPGAs found on e.g. Sipeed Tang Nano boards (very cheap on AliExpress) - a vendor called QuickLogic made SoCs that only use the FOSS toolchain for the FPGA part, out of the box: https://www.quicklogic.com/products/soc/eos-s3-microcontroller/ https://www.quicklogic.com/products/soc/eos-s3-microcontroll...
  - throwmeawaysoon 5y ago
    >Lattice has been by far the favorite of the FOSS community i'm interested in the OSS flows but i haven't dug in yet. so some questions (if you have experience): isn't it only for their ice40 chips? and how smooth is the flow from RTL to bitstream to deploy? one hesitation i have with jumping in is that i'm working on accelerator type stuff, so my designs typically need on the other of 30k-50k LUTs. will yosys+nextpnr let me deploy such a design to some chip?
    - floatboth 5y ago
      I don't have that much experience (don't really have many use cases for FPGAs personally tbh) but: Icestorm is for iCE40, Trellis is for ECP5 (which comes in variants up to 85k LUTs); the flow is simple enough to do manually but there are things that make it one-click. This tutorial series https://youtube.com/playlist?list=PLEBQazB0HUyT1WmMONxRZn9NmQ_9CIKhb https://youtube.com/playlist?list=PLEBQazB0HUyT1WmMONxRZn9Nm... uses one. As for handling really big designs, I don't know.