If you want some reading about boot flow, see e.g. https://www.coreboot.org/images/2/23/Apollolake_SoC.pdf https://www.coreboot.org/images/2/23/Apollolake_SoC.

If you want some reading about boot flow, see e.g. https://www.coreboot.org/images/2/23/Apollolake_SoC.pdf https://www.coreboot.org/images/2/23/Apollolake_SoC.pdf https://blogs.coreboot.org/blog/2019/07/17/gsoc-how-to-run-c-code-in-bootblock-stage-for-qemu-aarch64/ https://blogs.coreboot.org/blog/2019/07/17/gsoc-how-to-run-c... https://9esec.io/blog/open-source-cache-as-ram-with-intel-bootguard/ https://9esec.io/blog/open-source-cache-as-ram-with-intel-bo... The TLDR is that you need to get DRAM running before you can use it (e.g. by poking at DRAM controller's registers until it knows how to talk to your stick of RAM reliably and at a comfortable speed). Until then, you're stuck with SRAM. On ARM SoCs and Intel Apollo Lake, you use addressable SRAM. On most other x86 systems you use cache as RAM. Cache is just SRAM though, and the only difference between ARM and typical x86's case is that the latter doesn't let you directly address it. You can find examples of DDR DRAM configuration in u-boot sources, and presumably in coreboot too.