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Transistors actually keep getting smaller. 7nm->5nm devices got smaller. The transistors actually got significantly faster too. A lot of the problems are in wir

Transistors actually keep getting smaller. 7nm->5nm devices got smaller. The transistors actually got significantly faster too. A lot of the problems are in wiring and powering the things, leakage, etc. so that's where more innovation is needed. But the leading edge is far from standing still. I GAA and such pan out well that could be a very significant bump for the next few nodes. People act like everything stopped because "Moore's law is dead", but when you look at the rates of improvement in most other manufacturing sectors, semiconductors are still advancing at an enviable pace.

nwiswell 5y ago
> People act like everything stopped because "Moore's law is dead" This is really not what I said anywhere. What I said is that the pace of advancement is slower now, and that process supremacy is no longer sufficient to guarantee performance supremacy. That's a problem for Intel, since it was a core assumption of their business model.
MayeulC 5y ago
Dennard's scaling is long dead[1]. Density increases thanks to "3D" integration, but transistors do not shrink much. Thus more innovation needed in the areas you highlighted to make a "smaller" equivalent process node. FinFET and GAA do achieve slightly better electrostatic control which results in lower leakage and slightly faster switching speeds, but gate length doesn't decrease much anymore, which puts a ceiling on switching speed improvements (thus frequency - GHz), and gate capacitance (linked to power consumption). Increasing densities mean more avenues to explore specialized circuitry and dark silicon. Basically, more transistor to play with. This is running very contrary to the previous paradigm with Moore's Law, in which specialized circuitry and specialized accelerators were not too deeply investigated as software implementations would gain so much performance that they would easily surpass them, while not needing to be redesigned for a newer node. I'm now hoping for (and expecting) a revolution in maskless lithography at some point. That would democratize ASIC design (at 14nm, current multi-project wafers prototyping costs are around 10k€/mm², largely due to mask manufacturing), and make it much easier to explore the third dimension (thus making everyone more competitive with last gen). [1]: https://en.wikipedia.org/wiki/Dennard_scaling#Breakdown_of_Dennard_scaling_around_2006 https://en.wikipedia.org/wiki/Dennard_scaling#Breakdown_of_D... (although that article is a bit terrible).
- throwawaylinux 5y ago
  I know what Dennard scaling is, that's not what anybody is referring to when talking about process improvements. The technology has improved since then. And it will continue to improve.
  - MayeulC 5y ago
    Right (I'm also providing links for other readers). However, when mentioning the "nanometers" process node as evidence for scaling (it was unclear to me whether you said that it implied shrinking, or there had been some shrinking in between the two), I feel like I have to mention that transistors haven't been meaningfully shrunk for years, although there have been plenty of innovations regarding their layout, and photolithography processes have gained in precision. Transistors are still at the hearts of ICs, so every bit of efficiency gained there has tremendous impacts on system-level performance and efficiency. Some of the biggest possible gains on the horizon might come from circuit designs, notably adiabatic computing.
    - throwawaylinux 5y ago
      > However, when mentioning the "nanometers" process node as evidence for scaling (it was unclear to me whether you said that it implied shrinking, or there had been some shrinking in between the two), No, my intention was actually converse of that, saying that transistors still shink, even in leading edge nodes today, despite popular perception. > I feel like I have to mention that transistors haven't been meaningfully shrunk for years, although there have been plenty of innovations regarding their layout, and photolithography processes have gained in precision. TSMC 7nm->5nm increased transistor density by 80%. There were other changes to minimum cell size too, but both are 6T in this case so the overall device that can operate as a transistor in a VLSI does absolutely shrink. Dennard scaling ending isn't about not shrinking, it's about power density going up. Even then things are not standing still, practical designs absolutely get denser and do more work even in the logic parts of the design. It's just doesn't double every couple of years anymore.

nwiswell 5y ago

> People act like everything stopped because "Moore's law is dead" This is really not what I said anywhere. What I said is that the pace of advancement is slower now, and that process supremacy is no longer sufficient to guarantee performance supremacy. That's a problem for Intel, since it was a core assumption of their business model.

MayeulC 5y ago

Dennard's scaling is long dead[1]. Density increases thanks to "3D" integration, but transistors do not shrink much. Thus more innovation needed in the areas you highlighted to make a "smaller" equivalent process node. FinFET and GAA do achieve slightly better electrostatic control which results in lower leakage and slightly faster switching speeds, but gate length doesn't decrease much anymore, which puts a ceiling on switching speed improvements (thus frequency - GHz), and gate capacitance (linked to power consumption). Increasing densities mean more avenues to explore specialized circuitry and dark silicon. Basically, more transistor to play with. This is running very contrary to the previous paradigm with Moore's Law, in which specialized circuitry and specialized accelerators were not too deeply investigated as software implementations would gain so much performance that they would easily surpass them, while not needing to be redesigned for a newer node. I'm now hoping for (and expecting) a revolution in maskless lithography at some point. That would democratize ASIC design (at 14nm, current multi-project wafers prototyping costs are around 10k€/mm², largely due to mask manufacturing), and make it much easier to explore the third dimension (thus making everyone more competitive with last gen). [1]: https://en.wikipedia.org/wiki/Dennard_scaling#Breakdown_of_Dennard_scaling_around_2006 https://en.wikipedia.org/wiki/Dennard_scaling#Breakdown_of_D... (although that article is a bit terrible).

throwawaylinux 5y ago
I know what Dennard scaling is, that's not what anybody is referring to when talking about process improvements. The technology has improved since then. And it will continue to improve.
- MayeulC 5y ago
  Right (I'm also providing links for other readers). However, when mentioning the "nanometers" process node as evidence for scaling (it was unclear to me whether you said that it implied shrinking, or there had been some shrinking in between the two), I feel like I have to mention that transistors haven't been meaningfully shrunk for years, although there have been plenty of innovations regarding their layout, and photolithography processes have gained in precision. Transistors are still at the hearts of ICs, so every bit of efficiency gained there has tremendous impacts on system-level performance and efficiency. Some of the biggest possible gains on the horizon might come from circuit designs, notably adiabatic computing.
  - throwawaylinux 5y ago
    > However, when mentioning the "nanometers" process node as evidence for scaling (it was unclear to me whether you said that it implied shrinking, or there had been some shrinking in between the two), No, my intention was actually converse of that, saying that transistors still shink, even in leading edge nodes today, despite popular perception. > I feel like I have to mention that transistors haven't been meaningfully shrunk for years, although there have been plenty of innovations regarding their layout, and photolithography processes have gained in precision. TSMC 7nm->5nm increased transistor density by 80%. There were other changes to minimum cell size too, but both are 6T in this case so the overall device that can operate as a transistor in a VLSI does absolutely shrink. Dennard scaling ending isn't about not shrinking, it's about power density going up. Even then things are not standing still, practical designs absolutely get denser and do more work even in the logic parts of the design. It's just doesn't double every couple of years anymore.