> RISC-V seems to me to have two major opportunities. > - Where a free ISA allows innovation and experimentation in a way that Arm would not permit. I would s

> RISC-V seems to me to have two major opportunities. > - Where a free ISA allows innovation and experimentation in a way that Arm would not permit. I would say that the two major innovations of RISC-V are: - Composability. - Extensibility (that also fosters experimentation). Each ARM version X.Y comes with a license and with a condition: «thou shalt taketh either everything or nothing»; RISC-V has neither a license nor strings attached and is «thou may useth only what thou needeth». Anyone who does not need SIMD or the vector processing can do away with them in the silicon. It saves the die size[0] and costs. This is the composability aspect. Extensions planned out and/or reserved for future use (e.g. 128-bit extension of RISC-V), and the ability to add custom instructions to experiment with (and possible contribute to the RISC-V forum). This is the extensibility aspect. Other existing open ISA (MIPS, POWER SuperH J-2? – unsure on the status of the last one) do not offer composability and extensibility capabilities, which leads me to reason that it is the major innovation(s) of RISC-V. [0] Albeit it is somewhat fraught with the danger of creating a highly fragmented RISC-V CPU market where the software has to accommodate every possible permutation of RISC-V extensions and inject an emulation layer for extensions missing in the die.