But if it takes more cycles to calculate the output than input it into the system, wouldn't you have a problem? Others mentioned that they each have their own

But if it takes more cycles to calculate the output than input it into the system, wouldn't you have a problem? Others mentioned that they each have their own ring oscillator and that makes more sense. There is no _central_ clock, and each core has it's own memory. This also would mean there's no central bus. It's an intriguing design, I'm not totally sure I'm sold, but it definitely reduces some complexity.