Agreed... it's interesting but the eval board isn't $500 interesting. Looking at rough numbers, it seems to be possible to do anywhere from a 2x2 to 5x5 grid o

Agreed... it's interesting but the eval board isn't $500 interesting. Looking at rough numbers, it seems to be possible to do anywhere from a 2x2 to 5x5 grid of small RISC-V cores (with at least 2-4K of sysMEM) on an ECP5 FPGA, depending on model and softcore size, and the programming model would have a wider audience.