Oh, word. Thanks for the correction. I guess I extrapolated too much from the combo of you knowing enough of the clock inputs to the peripherals to make them

Oh, word. Thanks for the correction. I guess I extrapolated too much from the combo of you knowing enough of the clock inputs to the peripherals to make them work and a statement of yours about finding a pll bypass signal. I want to say your main point your statements on the pll bypass was that the cores must be mainly static logic because they ran stable at whatever rate the crystal is, but I'm half remembering and could conflating that with something else.