5 ms·

Author here if anyone has questions about IBM System/360 computers :-)

by kens 5y ago

boothby 5y ago
I'm trying to understand how they read out that BCROS memory. From the picture, it appears to be a single layer of copper on a mylar sheet. How did they get the bits out?
- kens 5y ago
  They read the data capacitively. A sheet with perpendicular drive lines was put on top of the copper sheet. Energizing a drive line capacitively coupled to the square capacitors on the BCROS sheet. Each bit had two capacitors (balanced), driving a differential amplifier (sense amplifier) to produce the output bit. Using two capacitors reduced noise since the differential amplifier would cancel out the noise.
  - boothby 5y ago
    Thanks, for the answer, and for maintaining the coolest website on the net. Keep up the good work!
monocasa 5y ago
I've heard from someone that used one that the 360/91 was microcoded, just very differently both compared to contemporaries and to today's machines. That the fetch, decode, and dispatch was in pure logic, but the execution units themselves (at least in the float unit, which was the only unit that was out of order) ran their own microcode programs. You wouldn't happen to know where more documents than what's on bitsavers exist for the 360/91 (or related like the 95 and 195) do you? Competing anecdotes are less than satisfying. My source has been worng before but he bats a pretty good average for his contrarian comparch statements.
- kens 5y ago
  Here's a very detailed paper on the 360/91 architecture: https://www.engineering.iastate.edu/~zzhang/cpre581/reading/ibm67-anderson-360.pdf https://www.engineering.iastate.edu/~zzhang/cpre581/reading/...
  - monocasa 5y ago
    That's a great paper! I really appreciate you finding that; it was a great read and does go further in depth than the funcChar docs. It unfortunately doesn't seem to disambiguate the specific question of if floating point execution units were implemented via microcode unless I'm missing it.
- pinewurst 5y ago
  I don't think the Mod 91 ever shipped. It was a combat machine designed to squash CDC (IBM was sued by them for their anti-competitive actions here) and was eventually transmogrified into the Mod 95/195 which did ship.
  - monocasa 5y ago
    According to wiki, there were 15 model 91s, 4 kept by IBM and the rest went to customers including NASA. There were two 95s and both went to NASA (and really the 95 was a 91 with a different RAM technology but the same CPU). That lines up with my source who started his career doing simulation and analysis of rocket propellent in micro gravity for the tail end of the Apollo program and some of the initial work for the space shuttle.
  - kens 5y ago
    There were approximately 15 Model 91s produced. The Computer History Museum has the console from one, and the Living Computers Museum has another. The Model 95 was the even more rare version with thin-film memory instead of core memory. Only two of them were produced, for NASA. The Model 195 was a reimplementation of the Model 91 with "monolithic" integrated circuits instead of hybrid SLT modules. The System 370/195 was very similar to the System 360/195. Curiously, the System 360/195 has the black styling of System/370 control panels, rather than the beige control panel of System/360. https://en.wikipedia.org/wiki/IBM_System/360_Model_91#Models_built https://en.wikipedia.org/wiki/IBM_System/360_Model_91#Models...
    - pinewurst 5y ago
      Thanks - I was probably thinking of the 90, 70, and some of the other promised 360s.
colejohnson66 5y ago
The IO "channels" are interesting. Are they analogous to the PIO in the RP2040 (Pi Pico)?
- kens 5y ago
  The System/360 I/O channels are kind of like a DMA (direct memory access) controller, so I/O can happen in the background instead of making the CPU wait. The Raspberry Pi PIO is more of a programmable state machine for low-level I/O protocols. So they are kind of similar in that they offload I/O tasks from the main CPU. But they also act at different levels: a System/360 channel does something like reading a block of data from tape, while a PIO deals with individual up and down transitions on a line.
  - bogomipz 5y ago
    Is this I/O channel architecture basically the same thing that makes mainframes so reliable even today? Might you or anyone else have any recommendations on mainframe I/O architecture evolution? I've tried to look it up in the past but without much success.
    - chiph 5y ago
      They are reliable through exhaustive testing of components, plus error-checking, plus redundancy (on some models). What channels get you is high I/O throughput. Especially in 80 character long records The machines (were and maybe still) are optimized to run COBOL, and what COBOL programs are commonly used for is operations like "Read a record, use columns 50 thru 59 to add to a total, repeat until EOF. Then print the total formatted as $**9,999.99" So the faster you can read records in, the better. Channels also did buffering when reading from devices like tape drives that did not like to start/stop their motion a lot. So the channel controller would tell the tape drive to read "a few" records and hold them for when the CPU asked for them. Mechanically, the tape reel would slow to a stop and a vacuum column would hold excess tape. The inertia of the reel did not allow for sudden starts/stops and if you tried you'd snap the tape. Curious Marc has a video: https://www.youtube.com/watch?v=7Lh4CMz_Z6M https://www.youtube.com/watch?v=7Lh4CMz_Z6M
j_not_j 5y ago
I wonder how the designers "knew" or hoped that the S/360 instruction set was achievable with that hardware/microcode design. Was it sufficient to cover all the instructions? The floating point portion seems like a likely risk. (Perhaps, more likely, the microcode drafts were co-written with hardware designs so they had less risk of a failure.)
- kens 5y ago
  There's not really much risk. Because the S/360 was built from gates (SLT) rather than an integrated circuit, they could easily change the design if needed. (Even at a customer site!) It's not like a microprocessor chip that would require an expensive re-spin if something went wrong. So if they discovered they needed another micro-operation, they could just add it to the design. There are a few micro-operations that seem rather contrived, as if they realized it would really help performance to do this random combination of things.

Author here if anyone has questions about IBM System/360 computers :-)

by kens 5y ago

Author here if anyone has questions about IBM System/360 computers :-)

I'm trying to understand how they read out that BCROS memory. From the picture, it appears to be a single layer of copper on a mylar sheet. How did they get the bits out?

kens 5y ago
They read the data capacitively. A sheet with perpendicular drive lines was put on top of the copper sheet. Energizing a drive line capacitively coupled to the square capacitors on the BCROS sheet. Each bit had two capacitors (balanced), driving a differential amplifier (sense amplifier) to produce the output bit. Using two capacitors reduced noise since the differential amplifier would cancel out the noise.
- boothby 5y ago
  Thanks, for the answer, and for maintaining the coolest website on the net. Keep up the good work!

monocasa 5y ago

I've heard from someone that used one that the 360/91 was microcoded, just very differently both compared to contemporaries and to today's machines. That the fetch, decode, and dispatch was in pure logic, but the execution units themselves (at least in the float unit, which was the only unit that was out of order) ran their own microcode programs. You wouldn't happen to know where more documents than what's on bitsavers exist for the 360/91 (or related like the 95 and 195) do you? Competing anecdotes are less than satisfying. My source has been worng before but he bats a pretty good average for his contrarian comparch statements.

kens 5y ago
Here's a very detailed paper on the 360/91 architecture: https://www.engineering.iastate.edu/~zzhang/cpre581/reading/ibm67-anderson-360.pdf https://www.engineering.iastate.edu/~zzhang/cpre581/reading/...
- monocasa 5y ago
  That's a great paper! I really appreciate you finding that; it was a great read and does go further in depth than the funcChar docs. It unfortunately doesn't seem to disambiguate the specific question of if floating point execution units were implemented via microcode unless I'm missing it.
pinewurst 5y ago
I don't think the Mod 91 ever shipped. It was a combat machine designed to squash CDC (IBM was sued by them for their anti-competitive actions here) and was eventually transmogrified into the Mod 95/195 which did ship.
- monocasa 5y ago
  According to wiki, there were 15 model 91s, 4 kept by IBM and the rest went to customers including NASA. There were two 95s and both went to NASA (and really the 95 was a 91 with a different RAM technology but the same CPU). That lines up with my source who started his career doing simulation and analysis of rocket propellent in micro gravity for the tail end of the Apollo program and some of the initial work for the space shuttle.
- kens 5y ago
  There were approximately 15 Model 91s produced. The Computer History Museum has the console from one, and the Living Computers Museum has another. The Model 95 was the even more rare version with thin-film memory instead of core memory. Only two of them were produced, for NASA. The Model 195 was a reimplementation of the Model 91 with "monolithic" integrated circuits instead of hybrid SLT modules. The System 370/195 was very similar to the System 360/195. Curiously, the System 360/195 has the black styling of System/370 control panels, rather than the beige control panel of System/360. https://en.wikipedia.org/wiki/IBM_System/360_Model_91#Models_built https://en.wikipedia.org/wiki/IBM_System/360_Model_91#Models...
  - pinewurst 5y ago
    Thanks - I was probably thinking of the 90, 70, and some of the other promised 360s.

colejohnson66 5y ago

The IO "channels" are interesting. Are they analogous to the PIO in the RP2040 (Pi Pico)?

kens 5y ago
The System/360 I/O channels are kind of like a DMA (direct memory access) controller, so I/O can happen in the background instead of making the CPU wait. The Raspberry Pi PIO is more of a programmable state machine for low-level I/O protocols. So they are kind of similar in that they offload I/O tasks from the main CPU. But they also act at different levels: a System/360 channel does something like reading a block of data from tape, while a PIO deals with individual up and down transitions on a line.
- bogomipz 5y ago
  Is this I/O channel architecture basically the same thing that makes mainframes so reliable even today? Might you or anyone else have any recommendations on mainframe I/O architecture evolution? I've tried to look it up in the past but without much success.
  - chiph 5y ago
    They are reliable through exhaustive testing of components, plus error-checking, plus redundancy (on some models). What channels get you is high I/O throughput. Especially in 80 character long records The machines (were and maybe still) are optimized to run COBOL, and what COBOL programs are commonly used for is operations like "Read a record, use columns 50 thru 59 to add to a total, repeat until EOF. Then print the total formatted as $**9,999.99" So the faster you can read records in, the better. Channels also did buffering when reading from devices like tape drives that did not like to start/stop their motion a lot. So the channel controller would tell the tape drive to read "a few" records and hold them for when the CPU asked for them. Mechanically, the tape reel would slow to a stop and a vacuum column would hold excess tape. The inertia of the reel did not allow for sudden starts/stops and if you tried you'd snap the tape. Curious Marc has a video: https://www.youtube.com/watch?v=7Lh4CMz_Z6M https://www.youtube.com/watch?v=7Lh4CMz_Z6M

j_not_j 5y ago

I wonder how the designers "knew" or hoped that the S/360 instruction set was achievable with that hardware/microcode design. Was it sufficient to cover all the instructions? The floating point portion seems like a likely risk. (Perhaps, more likely, the microcode drafts were co-written with hardware designs so they had less risk of a failure.)

kens 5y ago
There's not really much risk. Because the S/360 was built from gates (SLT) rather than an integrated circuit, they could easily change the design if needed. (Even at a customer site!) It's not like a microprocessor chip that would require an expensive re-spin if something went wrong. So if they discovered they needed another micro-operation, they could just add it to the design. There are a few micro-operations that seem rather contrived, as if they realized it would really help performance to do this random combination of things.