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CHERI (Capability Hardware Enhanced RISC Instructions) extends conventional hardware Instruction-Set Architectures (ISAs) with new architectural features to ena
by erwincoumans 5y ago
CHERI (Capability Hardware Enhanced RISC Instructions) extends conventional hardware
Instruction-Set Architectures (ISAs) with new architectural features to enable fine-grained
memory protection and highly scalable software compartmentalization.
- cbsmith 5y agoAlternatively, you could say it brings good ol' tagged memory architectures back from the dust bin of history. ;-)
- transpute 5y agoWe may see Arm's MTE (memory tagging extensions) [1] on 2022 Apple SoCs [1] https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/enhancing-memory-safety https://community.arm.com/arm-community-blogs/b/architecture...
- gumby 5y agoRISC-V has a tagging option.
- cbsmith 5y agoAt what point do we stop using the term RISC (particularly amusing is using it in CHERI since it's a nested acronym), when we're adding stuff to the ISA that used to be considered too much even for CISC architectures? ;-)
- gumby 5y agoYour characterization of tagging being “too much even for CISC architectures” doesn’t fit with my memory of processor development in the 80s and 90s back when I used to care about such things. Tagging originated in the 1960s far before the 801. Tagging can also mean two different things; one is a privileged control over part of the word (basically capabilities) and the other a user space option for pointer or immediate typing. Both can be handy and can benefit from hardware support.