3 ms·

Cheri C/C++ Programming Guide [pdf]

96 points by mzs 5y ago

erwincoumans 5y ago
CHERI (Capability Hardware Enhanced RISC Instructions) extends conventional hardware Instruction-Set Architectures (ISAs) with new architectural features to enable fine-grained memory protection and highly scalable software compartmentalization.
- cbsmith 5y ago
  Alternatively, you could say it brings good ol' tagged memory architectures back from the dust bin of history. ;-)
  - transpute 5y ago
    We may see Arm's MTE (memory tagging extensions) [1] on 2022 Apple SoCs [1] https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/enhancing-memory-safety https://community.arm.com/arm-community-blogs/b/architecture...
  - gumby 5y ago
    RISC-V has a tagging option.
    - cbsmith 5y ago
      At what point do we stop using the term RISC (particularly amusing is using it in CHERI since it's a nested acronym), when we're adding stuff to the ISA that used to be considered too much even for CISC architectures? ;-)
      - gumby 5y ago
        Your characterization of tagging being “too much even for CISC architectures” doesn’t fit with my memory of processor development in the 80s and 90s back when I used to care about such things. Tagging originated in the 1960s far before the 801. Tagging can also mean two different things; one is a privileged control over part of the word (basically capabilities) and the other a user space option for pointer or immediate typing. Both can be handy and can benefit from hardware support.
monocasa 5y ago
Very recent related conversation concerning the recent CHERI development systems: https://news.ycombinator.com/item?id=30007474 https://news.ycombinator.com/item?id=30007474 https://news.ycombinator.com/item?id=30007354 https://news.ycombinator.com/item?id=30007354
MaxBarraclough 5y ago
Briefly discussed August 2020: https://news.ycombinator.com/item?id=24114402 https://news.ycombinator.com/item?id=24114402 To restate my comment from that thread: here's the CHERI project home-page, which may be more approachable than the paper: https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/ https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/
- transpute 5y ago
  The Cheri-QEMU emulator is available for experimentation, https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri-qemu.html https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri...

96 points by mzs 5y ago

CHERI (Capability Hardware Enhanced RISC Instructions) extends conventional hardware Instruction-Set Architectures (ISAs) with new architectural features to enable fine-grained memory protection and highly scalable software compartmentalization.

cbsmith 5y ago
Alternatively, you could say it brings good ol' tagged memory architectures back from the dust bin of history. ;-)
- transpute 5y ago
  We may see Arm's MTE (memory tagging extensions) [1] on 2022 Apple SoCs [1] https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/enhancing-memory-safety https://community.arm.com/arm-community-blogs/b/architecture...
- gumby 5y ago
  RISC-V has a tagging option.
  - cbsmith 5y ago
    At what point do we stop using the term RISC (particularly amusing is using it in CHERI since it's a nested acronym), when we're adding stuff to the ISA that used to be considered too much even for CISC architectures? ;-)
    - gumby 5y ago
      Your characterization of tagging being “too much even for CISC architectures” doesn’t fit with my memory of processor development in the 80s and 90s back when I used to care about such things. Tagging originated in the 1960s far before the 801. Tagging can also mean two different things; one is a privileged control over part of the word (basically capabilities) and the other a user space option for pointer or immediate typing. Both can be handy and can benefit from hardware support.

monocasa 5y ago

Very recent related conversation concerning the recent CHERI development systems: https://news.ycombinator.com/item?id=30007474 https://news.ycombinator.com/item?id=30007474 https://news.ycombinator.com/item?id=30007354 https://news.ycombinator.com/item?id=30007354

MaxBarraclough 5y ago

Briefly discussed August 2020: https://news.ycombinator.com/item?id=24114402 https://news.ycombinator.com/item?id=24114402 To restate my comment from that thread: here's the CHERI project home-page, which may be more approachable than the paper: https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/ https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/

transpute 5y ago
The Cheri-QEMU emulator is available for experimentation, https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri-qemu.html https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/cheri...