3 ms·

Ambiq Apollo: There is a benchmark for these low power chips: https://www.eembc.org/ulpmark/ulp-cp/scores.php https://www.eembc.org/ulpmark/ulp-cp/scores.php

Ambiq Apollo: There is a benchmark for these low power chips: https://www.eembc.org/ulpmark/ulp-cp/scores.php https://www.eembc.org/ulpmark/ulp-cp/scores.php (click on the headers to sort..) I think Apollo is the most general purpose of these chips, even though it no longer gets the top score. I assume the RSL10 is using its DSP, and the R7F0E01182CFP is Cortex-M0+ (no floating). I used it for a project: the peripherals are really nice. For example, the I2C slave uses a shared memory design instead of waking up the CPU to receive anything.

kragen 5y ago
Thank you! How much power does it really use in practice? I haven't had the chance to test one myself. What does ULPMark-CPX of 705 mean? I assume it must be a measurement of some kind of computation per joule, since it's higher at lower voltages, but is the actual power consumption computable from it? Or is that only how much power it uses in deep sleep? Are those other chips also using subthreshold logic? Maybe https://www.eembc.org/ulpmark/ulp-cm/scores.php https://www.eembc.org/ulpmark/ulp-cm/scores.php is the actual power consumption used for computation (or rather vice versa: "number of CoreMark iterations a device can execute per milli-Joule" according to), which doesn't seem to include the Ambiq chips yet. I have the impression that a CoreMark is typically about 2 Dhrystone MIPS, which is not dimensionally compatible with the above.
- jhallenworld 5y ago
  How much: it was really low, and easier to get it in practice compared with ST's STM32L chips. I wonder if ST's new U series is using some kind of sub-threshold logic, but I assume Ambiq has the patents..
  - kragen 5y ago
    There's a lot of subthreshold research done over the last 20 years, a lot of it not by Ambiq, and I imagine that Ambiq has avoided patenting a lot of the stuff they've discovered in hopes of being able to protect it for longer as a trade secret. And I think subthreshold isn't really relevant to sleep-mode power consumption except in the sense that it might lower the consumption of your RTC or PWM or whatever. There have been a couple of experimental processors on which professors have published papers claiming an order of magnitude lower power consumption than Ambiq claims for their chips. Assuming that's true, I don't know how much of that is a question of process variability (e.g., maybe 5% of Ambiq's chips also get such low power consumption) and how much is a question of other engineering compromises (e.g., maybe ARM is a particularly power-hungry architecture, as the lower power consumption of the GD32VF chips suggests, or maybe the experimental chips only worked between 47° and 47.5° and even then they crashed once an hour). By "really low" do you mean active power more like 1 microwatt, 10 microwatts, 100 microwatts, or a milliwatt?
    - jhallenworld 5y ago
      So this was Apollo 1 at 3.3v: I think it was less than 3 milliwatts at full power, but easily below 1 microwatt when sleeping. For our design, I kept it mostly asleep. I also used Apollo 2, not quite as low power, but faster, better UART and it had more RAM and flash. For the UART: they added a timer to give you an interrupt when no more bytes were received (otherwise there was no interrupt because the Rx FIFO was not full). What I liked is that all peripherals were "low power"- all of them could work when the CPU was off and all could wake the CPU (well it woke on any pending interrupt). So it means it's more likely that the CPU is asleep. With STM32L, only peripherals designated low power would work while the CPU was off.
      - kragen 5y ago
        Hmm, my first thought was, "Wow, 3000 microwatts is pretty disappointing; that's in the same ballpark as STM32L or even AVR8, though presumably the Apollo 1 was several times faster than the STM32L. I wonder if their newer chips are better; the datasheets sure claim they are." But actually that number is totally in keeping with what I'd gotten from the Apollo3 datasheet: 33 pJ per Dhrystone "instruction" at 48 MHz and 1.25 DMIPS/MHz is 1.98 mW, and then there's 0.22 mW overhead, so we'd expect about 2.2 mW. 3 is close enough, especially for an earlier-generation chip. You might get an STM32L or an ATMega328 down to a milliwatt or two in run mode, but what (theoretically!) distinguishes the Ambiq chips is not their maximum power draw, but their efficiency per instruction and their deep power down load, which is what determines their power draw at a given computational load. Limited low-power peripherals can be a huge headache, yeah. Thank you very much for sharing your knowledge!

kragen 5y ago

Thank you! How much power does it really use in practice? I haven't had the chance to test one myself. What does ULPMark-CPX of 705 mean? I assume it must be a measurement of some kind of computation per joule, since it's higher at lower voltages, but is the actual power consumption computable from it? Or is that only how much power it uses in deep sleep? Are those other chips also using subthreshold logic? Maybe https://www.eembc.org/ulpmark/ulp-cm/scores.php https://www.eembc.org/ulpmark/ulp-cm/scores.php is the actual power consumption used for computation (or rather vice versa: "number of CoreMark iterations a device can execute per milli-Joule" according to), which doesn't seem to include the Ambiq chips yet. I have the impression that a CoreMark is typically about 2 Dhrystone MIPS, which is not dimensionally compatible with the above.

jhallenworld 5y ago
How much: it was really low, and easier to get it in practice compared with ST's STM32L chips. I wonder if ST's new U series is using some kind of sub-threshold logic, but I assume Ambiq has the patents..
- kragen 5y ago
  There's a lot of subthreshold research done over the last 20 years, a lot of it not by Ambiq, and I imagine that Ambiq has avoided patenting a lot of the stuff they've discovered in hopes of being able to protect it for longer as a trade secret. And I think subthreshold isn't really relevant to sleep-mode power consumption except in the sense that it might lower the consumption of your RTC or PWM or whatever. There have been a couple of experimental processors on which professors have published papers claiming an order of magnitude lower power consumption than Ambiq claims for their chips. Assuming that's true, I don't know how much of that is a question of process variability (e.g., maybe 5% of Ambiq's chips also get such low power consumption) and how much is a question of other engineering compromises (e.g., maybe ARM is a particularly power-hungry architecture, as the lower power consumption of the GD32VF chips suggests, or maybe the experimental chips only worked between 47° and 47.5° and even then they crashed once an hour). By "really low" do you mean active power more like 1 microwatt, 10 microwatts, 100 microwatts, or a milliwatt?
  - jhallenworld 5y ago
    So this was Apollo 1 at 3.3v: I think it was less than 3 milliwatts at full power, but easily below 1 microwatt when sleeping. For our design, I kept it mostly asleep. I also used Apollo 2, not quite as low power, but faster, better UART and it had more RAM and flash. For the UART: they added a timer to give you an interrupt when no more bytes were received (otherwise there was no interrupt because the Rx FIFO was not full). What I liked is that all peripherals were "low power"- all of them could work when the CPU was off and all could wake the CPU (well it woke on any pending interrupt). So it means it's more likely that the CPU is asleep. With STM32L, only peripherals designated low power would work while the CPU was off.
    - kragen 5y ago
      Hmm, my first thought was, "Wow, 3000 microwatts is pretty disappointing; that's in the same ballpark as STM32L or even AVR8, though presumably the Apollo 1 was several times faster than the STM32L. I wonder if their newer chips are better; the datasheets sure claim they are." But actually that number is totally in keeping with what I'd gotten from the Apollo3 datasheet: 33 pJ per Dhrystone "instruction" at 48 MHz and 1.25 DMIPS/MHz is 1.98 mW, and then there's 0.22 mW overhead, so we'd expect about 2.2 mW. 3 is close enough, especially for an earlier-generation chip. You might get an STM32L or an ATMega328 down to a milliwatt or two in run mode, but what (theoretically!) distinguishes the Ambiq chips is not their maximum power draw, but their efficiency per instruction and their deep power down load, which is what determines their power draw at a given computational load. Limited low-power peripherals can be a huge headache, yeah. Thank you very much for sharing your knowledge!