Because around the same time as intel started to experiment more with the AMT stuff, the complexity level of actually starting up the CPU and keeping it running

Because around the same time as intel started to experiment more with the AMT stuff, the complexity level of actually starting up the CPU and keeping it running had grown to the point where having an extra controller to help it run was found useful. Another reason is that ME (and PSP) are used to assert "security" of "Protected Media Path", which is part of streaming services DRM. It's not the only way to do it, sure, but there's a reason why IBM POWER designs have approximately 2.1x amount of cores that is stated in the spec - pretty much every core has a smaller, simpler one dedicated to keeping the big one running without melting and helping transition to low-power states and back, and there are at least two more cores whose only job is handling some of the early loading of code from flash. Part of why they have those cores is that since POWER8 there was a shift towards more standalone operation without external controller chip (and POWER9 even describes such boot process in manual). For comparison, traditionally the FSP (aka BMC) on IBM POWER systems initialized all of hardware before the CPU would execute first instruction, puppeting the CPU buses through debug interface.