14 ms·
5.5 mm in 1.25 nanoseconds
- theandrewbailey 5y agoI thought the later 360 CPUs were curiously designed. They had the 360 GPU integrated into the die, and had circuits that purposefully slowed things down to emulate separate chips. https://en.wikipedia.org/wiki/Xenon_(processor) https://en.wikipedia.org/wiki/Xenon_(processor)
- fredoralive 5y agoPresumably to ensure behaviour as near to identical as possible with earlier multi chip systems. Because they're fixed targets developers can end up coding right to the limits of console hardware, and end up with lots of reliance on exact timings etc. Xbox 360 was getting into the era where consoles had OSes and things should be abstracted through DirectX but I guess Microsoft decided the safest thing to do was create a clone with artificial slowdowns rather than risk games pushing the limit breaking. Nowadays consoles can change CPU / GPU microarchitectures seemingly without problems...
- Ciantic 5y ago> I got a copy of the detailed descriptions of the Xbox 360 CPU and I read it through multiple times This way of learning is not taught often enough, we learn it in school when learning another language (e.g. repeating words over and over). But in sciences and engineering the repeated reading of the material is not usually encouraged or talked about. It would be interesting to see what the material was, it's not linked, but it must have been really detailed.
- bostonsre 5y agoI think it depends alot on your rate of digestion (or understanding? can't find the right word...) of a piece of material. Being dropped in an alien book can make it tough to grasp everything on first pass. If you already have a lot of knowledge that links to the topics being discussed it is a lot easier to grok it in one pass.
- foobarian 5y agoSpecifically for CPU manuals, detailed reading used to pay off especially back when every cycle counted. You would spend days rereading tucked away sections describing some weird extension or edge case hoping to harness it for your game/program and get more speed out of it.
- Tepix 5y agoI used to read a lot of books when learning about computer science topics. I'm sure i've read the Camel book at least 4 times over several years. A well written book like that can really do much more than just provide a reference. A lot of documentation these days is mostly references that you look up when you need the nitty gritty details and the bigger picture is not documented as well.
- 123pie123 5y agothis is my standard way of learning stuff, I don't repeatedly read books just to memorise or remember stuff, but I repeatedly read books because you learn and fully digest certain concepts which are then needed before moving on to other concepts
- JasonFruit 5y agoThis is exactly it for me: on your first reading, there are underlying concepts you kind of get, but don't fully understand until you grasp what's built on top of them. Then, with that fuller grasp, you can go back and increase your understanding of the underlying material, which lets you understand the superstructure better — and the effect persists for several iterations if the topic is involved enough. Short version: don't be too concerned if you're not completely confident on the details the first time through, because it will make a lot more sense next time around.
- 123pie123 5y agoI also have the same approach for new projects I appologise in advance for the fact I will repeat questions to people and get it wrong initially, it's part of the learning process
- ehnto 5y agoI think rote memorization is less useful in engineering than critical thinking/problem solving, that is probably why. It's not really important you know X value of Y part by heart, you need to know how to get X value of any possible part you encounter. To learn a language, you can't problem solve your way to the solution, you either know it or you don't, and when you use it in practice (in a conversation) you can't look up what you need to know on the spot.
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- im3w1l 5y agoMemorizing facts is necessary to make them accessible to your critical thinking and problem solving though. Like it's much easier to find a connection between two things you know about compared to two things you could look up.
- wpietri 5y agoWe're not talking about rote memorization here. We're talking about deeply studying something. In the mid-90s I set up my then-employer's first WAN. Cisco 2501 with T1s for in-city links and frame relay for inter-city/international. As part of our Cisco contract, we got a full manual set, which was maybe 24" of shelf space. In my spare time over a couple of weeks, I sat down and read the whole thing. Then I went back and actually studied the parts that were relevant, mostly by reading and re-reading until it all made sense to me. On top of that, I added a lot of practical experimentation with the gear. But foundational for me was really understanding the perspective of the people who made it.
- wpietri 5y agoFor what it's worth, I think this "deep study" mode of learning is perhaps less useful today in tech. We have a lot more things we need to work with with now, and a searchable internet means we can draft off other people's learning a lot more. Deep understanding is both less possible and less useful for the bulk of us, who are mainly integrating lots of libraries, services, tools, and frameworks. But for every given topic, we still need deep experts, like Bruce Dawson was for this processor at Microsoft. So I think this mode is still very valuable, so I agree with Ciantic: this way of learning is something everybody should have at least some practice in.
- Cthulhu_ 5y agoIt depends, as always. A CPU is a whole unit, where (I think) it's worth knowing all the details. A programming language's standard library would be more about having a high level overview of what is available, and not a rote reading of all APIs. ...Unless you're into that kind of thing, and I do believe it will help "pick the right tool for the job", instead of writing your own or picking a random library off the internet. Maybe I should make a habit of it, I'm quite invested in Go at the moment. On the other hand, probably a bigger factor is 'arsedness'. I don't have the attention span or interest to read something back-to-front, or maybe not anymore? I don't know for sure. But there's not many things that grip me enough to really draw me in. ...except writing shitpost comments on HN.
- erosenbe0 5y agoYes, I teach my students to always at least look at the overview and see what is available and the taxonomy or ontology! Don't treat all sources as a mere dictionary of self-evident structure. Quitting just because the blurb of immediate interest has been rendered leaves out key opportunities to learn what is available.
- scoutt 5y ago> repeated reading of the material I taught myself almost everything I know, and repeated reading is the method I usually use. I don't memorize, but instead I attack any material to learn by "reading sweeps" (this only applies to topics I know nothing about). I first read all the material and, even if I don't understand a word about anything, I keep going until the end. Then I read everything again from start to end and here I can definitely say that I'm starting to understand. Then again, and this time I allow myself to go back and clarify something I didn't understand. When I feel confident, I try to implement something with the reading material at hand. I can't recall any material that I recently learnt that way but "The definitive guide to the ARM Cortex M3" by Joseph Yiu is a book I remember (back in 2007 when I started with Cortex microcontrollers).
- tomcam 5y agoImpressive. I’m just now learning how to learn that way, and I’m at retirement age. My way is much less efficient, because I stop and research each thing I don’t understand until I feel comfortable moving on. Highly inefficient, I now believe. My kid does what you do and learns way faster than I ever did.
- billti 5y agoThat the approach I've settled on that works best for me. I used to get frustrated that there wasn't "one source" of information that could take me on the journey from novice to expert, and that there was "so much to choose from" on most topics. Now I happily browse through as many sources as I can find, noting which I think are high quality even if above my head, and absorbing what I can for my current knowledge level. Then I'll revisit the good stuff and scan it to pick up the next layer deep, and repeat over select material until I feel I have what I need. The other thing I do is make flashcards as I go (I use an app called Quizlet, but I know there are lots out there). Especially with a new subject, just basic terms can be overwhelming at first. I capture want I feel is important in a question & answer format, and just fire it up when I have to a few mins to run through some flashcards (e.g. waiting for a meeting, sitting on the lav, etc.). It seems to work really well for me.
- brucedawson 5y agoThe material was all proprietary/NDA and I don't think it's ever been shared publicly, sorry. The main point I wanted to make with how I became the CPU expert was not actually the "reading multiple times" in order to deeply understand it (although that was important) but rather the fact that I chose to become the CPU expert rather than having it assigned to me. It was one of many times that I became the acknowledged expert of some area, and perhaps therefore in charge of that area, just by working hard in that area until I was "obviously" the expert.
- zeusk 5y agoYeah, I definitely echo this. I work on Display team in Windows and in past worked mostly on IddCx and SoftGpu but recently went through some VESA docs and chimed in my opinion during some meetings. Now I'm leading DisplayPort reliability efforts with graphics IHVs
- discreditable 5y agoI am blown away by the wafer of Xbox 360 CPUs hanging on this guy's wall. That was a kingly gift!
- bostonsre 5y agoAnyone know how much that would cost roughly? Wondering if they had a big reject bin that needed to be disposed of.
- andreareina 5y agoGuessing that the cost for a wafer at a state-of-the-art process has gone up over the years but not that much, in the vicinity of ~$10,000? https://twitter.com/chiakokhua/status/1306437988801486848 https://twitter.com/chiakokhua/status/1306437988801486848 sourced from https://cset.georgetown.edu/wp-content/uploads/AI-Chips%E2%80%94What-They-Are-and-Why-They-Matter.pdf https://cset.georgetown.edu/wp-content/uploads/AI-Chips%E2%8... p45
- bostonsre 5y agoPretty pricey for a plaque.. either they really liked him or they had some rejects I would guess.
- marcan_42 5y agoThey always have rejects. Actually, that's almost certainly an unfinished wafer. Modern flip chips don't look like that finished - you have an array of pads and power distribution covering all the cool features. I think there's a good chance that wafer doesn't have any metal layers, or only M1 at most. It looks the same as the chips I've delayered and removed all or almost all of the metal layers from. For example, here's a shot of the Wii's GPU with the metal layers scraped off: https://marcan.st/transf/hollywood_die.jpg https://marcan.st/transf/hollywood_die.jpg
- bowmessage 5y agoIt was always rumored around the FAB that dropping a case of wafers was akin to totaling a Ferrari. Maybe ~20 wafers in a case, so this math checks out!
- Tuna-Fish 5y agoSomewhat similar is Grace Hopper explaining the nanosecond: https://www.youtube.com/watch?v=9eyFDBPk4Yw https://www.youtube.com/watch?v=9eyFDBPk4Yw
- marcan_42 5y agoThe speed of light story is a fun conjecture, but given the discrepancy (30cm vs 5.5mm), I don't think that's it. Light travels slower in wires but not that much slower, and increased design clocks don't explain the discrepancy either. I think it's more likely that this is an artifact of the interconnect design. For example, the interconnect may be designed as a tree, where the path from core 0 to the L2 only visits a branch but the path to core1/2 has to traverse the root of the tree. If each stage adds a clock cycle, there's your 4 clock cycles: one to go to the root, one back down to the other side, and then the whole thing in the other direction for the reply from L2 with the data. If the interconnect had been a ring bus instead, you'd find that the latency from cores 0 and 2 is the same, but higher for core 1 - assuming no other endpoints in the ring, but that's obviously not the case, since I/O needs to be on the bus too. It's possible he got the core numbers wrong in the die shot, and core 0 is the bottom left core. Then if the ring goes clockwise L2 - core 0 - core 1 - core 2 - I/O on the top right - L2, that's how you end up with core 0 being closer to the L2 in terms of clock cycles than the others, and the observation would be consistent with this design too.
- 123pie123 5y agothis is an interesting video (to me anyway!!) on the speed of electrons vs fields The Big Misconception About Electricity.. https://www.youtube.com/watch?v=bHIhgxav9LY https://www.youtube.com/watch?v=bHIhgxav9LY
- Dumble 5y agohttps://www.youtube.com/watch?v=2Vrhk5OjBP8 https://www.youtube.com/watch?v=2Vrhk5OjBP8
- jaywalk 5y agoThat video is hilariously wrong, which seems to be a common theme for Veritasium lately. I can't tell if he legitimately believes what he's saying, or if he produces these seemingly-correct-but-not videos to drive up engagement and views.
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- cmpaul 5y agoTechnical aspects aside (and congrats on the achievement!), I love the implications of the author's "Aside": 1. An otherwise inconvenient situation (snowpocalypse) was turned into a learning opportunity. I would've probably turned it into a Netflix binge. 2. People took the time to detail the CPU design in a document. I'm always looking for examples showing the benefits of documenting design (I'm an EM) and it's rare to find one that changes someone's life trajectory. :)
- tomcam 5y agoAgreed. I’m a pathetically slow learner so situations like #1 were always an essential part of how I got ahead of the curve. #2 is very cool also... but what is an EM?
- brucedawson 5y ago2004 was a bit early for a Netflix binge. Plus, the power was out, so there goes that plan. The documentation that I read showed the pipelines in great deal, but they were badly presented such that the flows of data and time were obscured. My main contribution was to straighten out and simplify the diagrams, and then animate them. Well, and then explain them. It was definitely a CPU that required that level of detail.
- tom-thistime 5y agoSounds like mostly gate delay? I'll share my ignorance. For metal traces on silicon the physical "speed of light in this material" propagation delay should only be around 9-10 ns/m. Call it 10 ps/mm, about 55ps in 5.5mm. Or else if the trace has high enough resistance (maybe not metal), another thing to worry about is charging the line capacitance. That is longer for longer lines, but it is a different kind of delay from speed-of-light.
- nashashmi 5y agoI have seen these hang on someone's wall. Because they made the ATI cpu. I thought the whole thing was one big cpu. I was not impressed. Now I am! 15 years late.
- mattnewport 5y agoI was working on the central technology team at EA during the run up to the launch of the Xbox 360 and some of us got early access to help prepare for the new architecture. I was blown away by the amount of technical detail we were getting access to and how clearly explained it was. Much of that was thanks to Bruce Dawson. I remember devouring everything I could find that he'd written and it was a fascinating crash course in CPU architecture for a relatively young software engineer at the time with little hardware background. Thanks Bruce!
- mring33621 5y agoAll I want to say is that the XBOX 360 was one of the best consoles EVER! I still happily play games on mine.
- ridaj 5y agohttps://en.wikipedia.org/wiki/Signal_velocity https://en.wikipedia.org/wiki/Signal_velocity - my understanding is that the speed is driven by interactions between the trace and its surrounding material, which creates capacitance and inductance along the path
- jmrm 5y agoAt that distance, depending of the frequency of those buses, it could have some distortion and some latency due to being a transmission line. If this happened, the team that made that CPU would add some kind buffers at the receiving side to get the data at a correct time, and that could be most of the induced lag. Adding that to the fact that the three cores have a shared common bus, and there are gone to be some kind of signalling about who is using it (that we don't know), this could be reasonable. The Xbox 360 CPUs works at 3.2 GHz, that's 0.3125 ns per cycle, and four cycles make those 1.25 ns. I won't be surprised if those who made the CPU designed to have 4 cycles of delay to cores 1 and 2 to be sure there isn't any kind of glitch reading the data from the port.
- SeasonalEnnui 5y agoYou meant 0.3125ns per cycle, the rest of your comment triggered a thought: It's common in FPGA/microcontroller designs to have 'input synchronizers' on inputs from long digital lines (on any input where you can't guarantee synchronicity) to prevent metastability problems, especially when crossing clock domains. I think that's likely the case here, there are both long lines and different clock domains.
- jmrm 5y agoOops! Totally true: 0.3125 ns per cycle
- tomcam 5y agoThe post itself was a pleasure to read. The comments are a mini education on how to learn. I strongly recommend reading through both!
- rdlw 5y agoThis post should be retitled to "11 mm in 1.25 nanoseconds", the blog post has been renamed to that as per this update: "...So the 5.5 mm actually only takes 0.625 nanoseconds each way, the signal actually goes 11 mm in 1.25 nanoseconds, so the original title of this blog post is a lie. Sorry!"
- rq1 5y agoIsn’t the discrepancy due to https://en.m.wikipedia.org/wiki/Space-filling_curve https://en.m.wikipedia.org/wiki/Space-filling_curve ? (Aka Peano curves)