I'm not in EE, but I'd imagine that you start with x1 lane and work your way up. Each PCIe lane is an independent SERDES. Its not like a parallel memory contro

I'm not in EE, but I'd imagine that you start with x1 lane and work your way up. Each PCIe lane is an independent SERDES. Its not like a parallel memory controller where they share a clock, when you have x16 lanes, you have 16x independent streams you're shoving to the device downstream.