Theoretically, the E core can raise a #UD (undefined instruction) exception that the OS would trap (which already happens if the CPU doesn’t have AVX-512). The

Theoretically, the E core can raise a #UD (undefined instruction) exception that the OS would trap (which already happens if the CPU doesn’t have AVX-512). The OS could then detect that the offending instruction is from the AVX-512 set, and move it to a P core. It could even set a flag on the thread to force it to use P cores. Intel even touted the work they did with Microsoft about the scheduler to deal with selecting which E or P core to use. I’m not sure why they chose to disable AVX-512 instead of doing that. Maybe that is their end goal, but it’s too much effort to have it done by release.