4 ms·

I thought it was about delivering the clock signal to the processor (before the next cycle) ? As I understand you have to make circuits faster and smaller at t

• rbanffy 15y ago
  > still have time for clock distribution... We are talking about pretty radical processor designs. Why not go asynchronous if we are talking about coordinating multiple layers of silicon?
  • starwed 15y ago
    Wouldn't a principle advantage of an actual, innovative 3D chip be better component distribution? That is, on average all the parts will be much closer to each other, than if they were arranged on a 2D surface.
    • rbanffy 15y ago
      From the images, it appears inter-chip connections run over the external borders. This increases the distances signals have to travel and limits the width of the buses. I am not familiar with the technical limits of building vertical buses connecting the various chips glued together, but I assume 1000+ bit wide buses would not be impossible, so, although limited, the limits seem pretty high. Optical interconnects may also be possible in such confined devices. It will be interesting to watch. If real devices built with that technologies start showing in p and zSeries machines before 2015, we'll have some serious performance bump in high-end computers.