3 ms·

Sure there's value. The biggest obstacle to cranking up clock speed is heat dissipation. If we can get the heat away from the chip faster, we can increase the c

Sure there's value. The biggest obstacle to cranking up clock speed is heat dissipation. If we can get the heat away from the chip faster, we can increase the clock speed.

kisielk 15y ago
I still don't really see how it would help with heat dissipation overall. Most low power desktop CPUs seem to run at around 45W these days. If you stacked 10 of them, presumably you'd get somewhere around 450W. 100 of them would give you 4.5MW. First off, how do you get the electricity to power these, and secondly what do you do with the heat after it's left the CPU? For servers, you face the same problem. It's already possible to get power and heat density that is more than what your typical datacenter can handle. If the density increased by even 10 times we would presumably need some serious advances in cooling to be able to handle all those servers.
- merraksh 15y ago
  100x45W = 4.5 kW, not megawatt. 4.5 kilowatt is the same order of magnitude of a dryer.
swah 15y ago
I thought it was about delivering the clock signal to the processor (before the next cycle) ? As I understand you have to make circuits faster and smaller at the same time, so you still have time for clock distribution...
- rbanffy 15y ago
  > still have time for clock distribution... We are talking about pretty radical processor designs. Why not go asynchronous if we are talking about coordinating multiple layers of silicon?
  - starwed 15y ago
    Wouldn't a principle advantage of an actual, innovative 3D chip be better component distribution? That is, on average all the parts will be much closer to each other, than if they were arranged on a 2D surface.
    - rbanffy 15y ago
      From the images, it appears inter-chip connections run over the external borders. This increases the distances signals have to travel and limits the width of the buses. I am not familiar with the technical limits of building vertical buses connecting the various chips glued together, but I assume 1000+ bit wide buses would not be impossible, so, although limited, the limits seem pretty high. Optical interconnects may also be possible in such confined devices. It will be interesting to watch. If real devices built with that technologies start showing in p and zSeries machines before 2015, we'll have some serious performance bump in high-end computers.

Sure there's value. The biggest obstacle to cranking up clock speed is heat dissipation. If we can get the heat away from the chip faster, we can increase the clock speed.

kisielk 15y ago

I still don't really see how it would help with heat dissipation overall. Most low power desktop CPUs seem to run at around 45W these days. If you stacked 10 of them, presumably you'd get somewhere around 450W. 100 of them would give you 4.5MW. First off, how do you get the electricity to power these, and secondly what do you do with the heat after it's left the CPU? For servers, you face the same problem. It's already possible to get power and heat density that is more than what your typical datacenter can handle. If the density increased by even 10 times we would presumably need some serious advances in cooling to be able to handle all those servers.

merraksh 15y ago
100x45W = 4.5 kW, not megawatt. 4.5 kilowatt is the same order of magnitude of a dryer.

swah 15y ago

I thought it was about delivering the clock signal to the processor (before the next cycle) ? As I understand you have to make circuits faster and smaller at the same time, so you still have time for clock distribution...

rbanffy 15y ago
> still have time for clock distribution... We are talking about pretty radical processor designs. Why not go asynchronous if we are talking about coordinating multiple layers of silicon?
- starwed 15y ago
  Wouldn't a principle advantage of an actual, innovative 3D chip be better component distribution? That is, on average all the parts will be much closer to each other, than if they were arranged on a 2D surface.
  - rbanffy 15y ago
    From the images, it appears inter-chip connections run over the external borders. This increases the distances signals have to travel and limits the width of the buses. I am not familiar with the technical limits of building vertical buses connecting the various chips glued together, but I assume 1000+ bit wide buses would not be impossible, so, although limited, the limits seem pretty high. Optical interconnects may also be possible in such confined devices. It will be interesting to watch. If real devices built with that technologies start showing in p and zSeries machines before 2015, we'll have some serious performance bump in high-end computers.