3 ms·

So this is a way of dissipating heat more efficiently, such that chips can be apparently be stacked on top of each other -- does that really help all that much

by starwed 15y ago

So this is a way of dissipating heat more efficiently, such that chips can be apparently be stacked on top of each other -- does that really help all that much for consumer (and especially mobile) stuff? Seems like you're still generating the same total amount of heat, that needs venting from the machine. And still consuming the same amount of power. I'm sure there's some value here, but it's not going to arise from just stacking up the same chips we use today.

ramidarigaz 15y ago
Sure there's value. The biggest obstacle to cranking up clock speed is heat dissipation. If we can get the heat away from the chip faster, we can increase the clock speed.
- kisielk 15y ago
  I still don't really see how it would help with heat dissipation overall. Most low power desktop CPUs seem to run at around 45W these days. If you stacked 10 of them, presumably you'd get somewhere around 450W. 100 of them would give you 4.5MW. First off, how do you get the electricity to power these, and secondly what do you do with the heat after it's left the CPU? For servers, you face the same problem. It's already possible to get power and heat density that is more than what your typical datacenter can handle. If the density increased by even 10 times we would presumably need some serious advances in cooling to be able to handle all those servers.
  - merraksh 15y ago
    100x45W = 4.5 kW, not megawatt. 4.5 kilowatt is the same order of magnitude of a dryer.
- swah 15y ago
  I thought it was about delivering the clock signal to the processor (before the next cycle) ? As I understand you have to make circuits faster and smaller at the same time, so you still have time for clock distribution...
  - rbanffy 15y ago
    > still have time for clock distribution... We are talking about pretty radical processor designs. Why not go asynchronous if we are talking about coordinating multiple layers of silicon?
    - starwed 15y ago
      Wouldn't a principle advantage of an actual, innovative 3D chip be better component distribution? That is, on average all the parts will be much closer to each other, than if they were arranged on a 2D surface.
      - rbanffy 15y ago
        From the images, it appears inter-chip connections run over the external borders. This increases the distances signals have to travel and limits the width of the buses. I am not familiar with the technical limits of building vertical buses connecting the various chips glued together, but I assume 1000+ bit wide buses would not be impossible, so, although limited, the limits seem pretty high. Optical interconnects may also be possible in such confined devices. It will be interesting to watch. If real devices built with that technologies start showing in p and zSeries machines before 2015, we'll have some serious performance bump in high-end computers.
pork 15y ago
When large advances in processing power become cost-effective and widespread, programming paradigms will change to take advantage of the fact. Cases in point: the Cell processor and modern PS3 games that really take advantage of it, CUDA on graphics cards and all the scientific computing that is starting to shift to it, and even multi-core and the renewed interest in multithreaded programming.
marshray 15y ago
I don't see how stacking chips would do anything but make the heat dissipation problem much much worse. There is no magical "heat dissipating adhesive", only substances that conduct heat better or worse. A conventional chip is a thin planar heating element attached with maximal surface area to its heat sink and we have great trouble keeping them cool now. Heat generated internally a cubic object is more difficult to remove because the volume that is generating heat grows faster in proportion to the surface area available for removing it. I.e., the heat generation grows with the cube of the unit length and the surface only with the square). The worst shape of all is spherical which has the highest possible ratio of volume to surface area. Even if they managed to put heat sinks in contact with all six sides of this stack of dies, they could (at best) only remove six conventional chips' worth of heat. Unless they have a way of circulating liquid coolant through that volume, stacking chips like that is only practical if they're almost completely off.

by starwed 15y ago

ramidarigaz 15y ago

Sure there's value. The biggest obstacle to cranking up clock speed is heat dissipation. If we can get the heat away from the chip faster, we can increase the clock speed.

kisielk 15y ago
I still don't really see how it would help with heat dissipation overall. Most low power desktop CPUs seem to run at around 45W these days. If you stacked 10 of them, presumably you'd get somewhere around 450W. 100 of them would give you 4.5MW. First off, how do you get the electricity to power these, and secondly what do you do with the heat after it's left the CPU? For servers, you face the same problem. It's already possible to get power and heat density that is more than what your typical datacenter can handle. If the density increased by even 10 times we would presumably need some serious advances in cooling to be able to handle all those servers.
- merraksh 15y ago
  100x45W = 4.5 kW, not megawatt. 4.5 kilowatt is the same order of magnitude of a dryer.
swah 15y ago
I thought it was about delivering the clock signal to the processor (before the next cycle) ? As I understand you have to make circuits faster and smaller at the same time, so you still have time for clock distribution...
- rbanffy 15y ago
  > still have time for clock distribution... We are talking about pretty radical processor designs. Why not go asynchronous if we are talking about coordinating multiple layers of silicon?
  - starwed 15y ago
    Wouldn't a principle advantage of an actual, innovative 3D chip be better component distribution? That is, on average all the parts will be much closer to each other, than if they were arranged on a 2D surface.
    - rbanffy 15y ago
      From the images, it appears inter-chip connections run over the external borders. This increases the distances signals have to travel and limits the width of the buses. I am not familiar with the technical limits of building vertical buses connecting the various chips glued together, but I assume 1000+ bit wide buses would not be impossible, so, although limited, the limits seem pretty high. Optical interconnects may also be possible in such confined devices. It will be interesting to watch. If real devices built with that technologies start showing in p and zSeries machines before 2015, we'll have some serious performance bump in high-end computers.

pork 15y ago

When large advances in processing power become cost-effective and widespread, programming paradigms will change to take advantage of the fact. Cases in point: the Cell processor and modern PS3 games that really take advantage of it, CUDA on graphics cards and all the scientific computing that is starting to shift to it, and even multi-core and the renewed interest in multithreaded programming.

marshray 15y ago

I don't see how stacking chips would do anything but make the heat dissipation problem much much worse. There is no magical "heat dissipating adhesive", only substances that conduct heat better or worse. A conventional chip is a thin planar heating element attached with maximal surface area to its heat sink and we have great trouble keeping them cool now. Heat generated internally a cubic object is more difficult to remove because the volume that is generating heat grows faster in proportion to the surface area available for removing it. I.e., the heat generation grows with the cube of the unit length and the surface only with the square). The worst shape of all is spherical which has the highest possible ratio of volume to surface area. Even if they managed to put heat sinks in contact with all six sides of this stack of dies, they could (at best) only remove six conventional chips' worth of heat. Unless they have a way of circulating liquid coolant through that volume, stacking chips like that is only practical if they're almost completely off.