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Q32-17 may have 32 cores, may have 45W TDP and may have whooping 128 pcie 4.0 lanes but it is still only 1.7GHz. What this means in practice is that this will

Q32-17 may have 32 cores, may have 45W TDP and may have whooping 128 pcie 4.0 lanes but it is still only 1.7GHz. What this means in practice is that this will heavily depend on the type of load you are running. A lot of workstation type loads just can't make use of 32 threads and on that CPU it will have to just to offset for the slower single core performance.

PragmaticPulp 5y ago
The 1.7GHz boost speed is a significant limitation. Ignoring architecture differences for a moment, that’s about 1/2 the clock speed of something like an M1 or even a modern cell phone chip. It’s almost 1/3 of the boost clock of a modern Intel or AMD desktop chip. Given the choice and assuming equal cache sizes, I’d take a 3.4GHz version with 16 cores over a 1.7GHz version with 32 cores. The only time a higher core count with proportionally lower clock speed really helps is when you’re going for raw power efficiency.
windexh8er 5y ago
One application, where this type of processor makes sense, is network based middleboxes. Think of things like firewalls that have evolved to have a lot of different functionality and a need for a lot of simultaneous thread processing availability. This type of chip on a SmartNIC could be very popular. And while this is a bit niche I'm sure there are plenty of other use cases. E.g. nodes running a lot of FaaS containers, VPS providers looking to offer higher CPU count but lower clock speeds, etc.
bee_rider 5y ago
I'm thinking more as a developer machine to prepare for the future, rather than as a real productivity workstation. Assuming the predictions of ARM ascendancy actually come true (certainly remains to be seen) you should want your code to run well on 32 ARM cores @1.7GHz, because that means it'll run really well on the production workstations that come out in a couple years, right?
- wongarsu 5y ago
  If production workstations become ARM based, wouldn't it be more likely that we get 2-4 high-speed (3-4GHz) cores and a large number of low speed cores? That's analogous to smartphone architectures with their low-power cores and high-speed/high-power cores, and better matches how real-world workloads behave.
  - bee_rider 5y ago
    So the smaller cores could be more like throughput-tuned efficiency cores, rather than 100% power saving cores -- kind of like Alder Lake? Seems like a neat idea. Almost like a Xeon + Xeon Phi, but on a chip. Seem like that'd get around the communication issue of the Phi and probably the compatibility issues as well.
- zitterbewegung 5y ago
  Apple used an A12z bionic for people to prepare for M1 and their derivatives which has a big-little configuration . I don’t see this or any other server with this configuration at all. A ARM workstation would definitely have this which begs the question that a Mac with apple silicon would be the developer machine to prepare for the future .

PragmaticPulp 5y ago

The 1.7GHz boost speed is a significant limitation. Ignoring architecture differences for a moment, that’s about 1/2 the clock speed of something like an M1 or even a modern cell phone chip. It’s almost 1/3 of the boost clock of a modern Intel or AMD desktop chip. Given the choice and assuming equal cache sizes, I’d take a 3.4GHz version with 16 cores over a 1.7GHz version with 32 cores. The only time a higher core count with proportionally lower clock speed really helps is when you’re going for raw power efficiency.

windexh8er 5y ago

One application, where this type of processor makes sense, is network based middleboxes. Think of things like firewalls that have evolved to have a lot of different functionality and a need for a lot of simultaneous thread processing availability. This type of chip on a SmartNIC could be very popular. And while this is a bit niche I'm sure there are plenty of other use cases. E.g. nodes running a lot of FaaS containers, VPS providers looking to offer higher CPU count but lower clock speeds, etc.

bee_rider 5y ago

I'm thinking more as a developer machine to prepare for the future, rather than as a real productivity workstation. Assuming the predictions of ARM ascendancy actually come true (certainly remains to be seen) you should want your code to run well on 32 ARM cores @1.7GHz, because that means it'll run really well on the production workstations that come out in a couple years, right?

wongarsu 5y ago
If production workstations become ARM based, wouldn't it be more likely that we get 2-4 high-speed (3-4GHz) cores and a large number of low speed cores? That's analogous to smartphone architectures with their low-power cores and high-speed/high-power cores, and better matches how real-world workloads behave.
- bee_rider 5y ago
  So the smaller cores could be more like throughput-tuned efficiency cores, rather than 100% power saving cores -- kind of like Alder Lake? Seems like a neat idea. Almost like a Xeon + Xeon Phi, but on a chip. Seem like that'd get around the communication issue of the Phi and probably the compatibility issues as well.
zitterbewegung 5y ago
Apple used an A12z bionic for people to prepare for M1 and their derivatives which has a big-little configuration . I don’t see this or any other server with this configuration at all. A ARM workstation would definitely have this which begs the question that a Mac with apple silicon would be the developer machine to prepare for the future .