4 ms·

For our HPC workload these CPUs perform around 25% better than the AMD ones being compared. “Fast CPU is cheaper than slow CPU” is newsworthy.

josephg 5y ago
Great! That's what I want to know. Thankyou - Your comment is more informative for me than the article.
- rbanffy 5y ago
  Even if a Neoverse N1 core had a third of the performance of a Xeon core, the part has about 3x as many cores than a top-of-the-line Xeon for about 75% of the part price. After reading the article it is quite obvious this has a much higher performance per dollar than a Xeon for less.
slaymaker1907 5y ago
This makes sense to me since the x86 chips have the advantage of running a lot more software out of the box. Sure a lot of software can just be recompiled, but compiling for ARM can be very difficult for software doing a lot of low level performance tricks.
- maxwell86 5y ago
  HPC software is essentially always doing lots of low level performance tricks, using hardware-specific intrinsics, etc. Most of the hardcore libraries we use (vector math, linear algebra, networking, etc.) all support ARM with good performance, and for the code we maintain, we didn't really had to modify any code to run on ARM well. If you need to translate e.g. SSE intrinsics to ARM, there is an automatic translator available, but 10 years ago when we had to translate those to AVX, we decided instead to translate them to the portable compiler intrinsics instead (all compilers have portable vector types nowadays), so we didn't have to change anything. A 256-bit wide SIMD vector just gets treated as 2x 128 bit NEON vectors when compiling for ARM, and the compilers do this automatically.
bee_rider 5y ago
What kind of workloads do you have? I often wonder how these Ampere chips would do on sparse matrix operations. Potential for parallelism, but possibly less vector potential, to keep the GPUs away...
- maxwell86 5y ago
  classical memory bound engineering problems: solving sparse linear system of equations, stencil codes, etc. > sparse matrix operations. These are usually memory bound (otherwise they aren't really that sparse), and while most CPUs in the same price category offer similar bandwidth, our benchmarks achieve higher bandwidth.
  - bee_rider 5y ago
    I've had enough luck with Pardiso (my matrices have a nice structure, not too much fill-in after they do METIS or whatever, I guess) that the presence of a free copy of Intel's Pardiso spinoff in MKL is enough to keep me on x86. I don't think this generalizes, though -- the situation with Pardiso, where it is included in Intel's free library but paid for everywhere else (as far as I can tell), is a bit unusual.

josephg 5y ago

Great! That's what I want to know. Thankyou - Your comment is more informative for me than the article.

rbanffy 5y ago
Even if a Neoverse N1 core had a third of the performance of a Xeon core, the part has about 3x as many cores than a top-of-the-line Xeon for about 75% of the part price. After reading the article it is quite obvious this has a much higher performance per dollar than a Xeon for less.

slaymaker1907 5y ago

This makes sense to me since the x86 chips have the advantage of running a lot more software out of the box. Sure a lot of software can just be recompiled, but compiling for ARM can be very difficult for software doing a lot of low level performance tricks.

maxwell86 5y ago
HPC software is essentially always doing lots of low level performance tricks, using hardware-specific intrinsics, etc. Most of the hardcore libraries we use (vector math, linear algebra, networking, etc.) all support ARM with good performance, and for the code we maintain, we didn't really had to modify any code to run on ARM well. If you need to translate e.g. SSE intrinsics to ARM, there is an automatic translator available, but 10 years ago when we had to translate those to AVX, we decided instead to translate them to the portable compiler intrinsics instead (all compilers have portable vector types nowadays), so we didn't have to change anything. A 256-bit wide SIMD vector just gets treated as 2x 128 bit NEON vectors when compiling for ARM, and the compilers do this automatically.

bee_rider 5y ago

What kind of workloads do you have? I often wonder how these Ampere chips would do on sparse matrix operations. Potential for parallelism, but possibly less vector potential, to keep the GPUs away...

maxwell86 5y ago
classical memory bound engineering problems: solving sparse linear system of equations, stencil codes, etc. > sparse matrix operations. These are usually memory bound (otherwise they aren't really that sparse), and while most CPUs in the same price category offer similar bandwidth, our benchmarks achieve higher bandwidth.
- bee_rider 5y ago
  I've had enough luck with Pardiso (my matrices have a nice structure, not too much fill-in after they do METIS or whatever, I guess) that the presence of a free copy of Intel's Pardiso spinoff in MKL is enough to keep me on x86. I don't think this generalizes, though -- the situation with Pardiso, where it is included in Intel's free library but paid for everywhere else (as far as I can tell), is a bit unusual.