Thankfully that probability decreases exponentially as you add synchronizer stages, which is what you do for clock domain crossing :-). Two synchronizer stages

Thankfully that probability decreases exponentially as you add synchronizer stages, which is what you do for clock domain crossing :-). Two synchronizer stages will give you an MTBF on the order of the square of the age of the universe, by one ballpark calculation I found. This obviously goes down as you do it in parallel many times, but still, we're pretty safe here in practice. I clearly remember having modified/written an FPGA logic analyzer that ended up entering impossible logic lockup states after a few minutes/seconds (Hardware, crashing? What?)... that was when I learned about metastability. Some synchronizers took care of the problem.