TSMC claims 15% higher clocks OR 20% lower power for the same architecture moving from N7 to N5. There's a HUGE asterisk sitting somewhere and I'm pretty sure I

TSMC claims 15% higher clocks OR 20% lower power for the same architecture moving from N7 to N5. There's a HUGE asterisk sitting somewhere and I'm pretty sure I know where. https://www.anandtech.com/show/12727/tsmc-details-5-nm-process-tech-aggressive-scaling-but-thin-power-and-performance-gains https://www.anandtech.com/show/12727/tsmc-details-5-nm-proce... Chips with loads of cores like Milan (the one mentioned in that article) have very low clockspeeds to keep down the TDP. I'd guess that their 2.2-3GHz clocks are easily possible with high-density designs (high-density usually going hand-in-hand with lower clockspeeds), so performance won't suffer and might even improve due to shifting power savings into slightly higher clocks. That's the upside, but there is also a definite downside. Desktop chip clockspeeds will suffer. If they are made on these processes, they simply will not be able to achieve those high clocks (probably 3.5-4GHz at the absolute top end). That means that even if Zen 4 gets a 20% IPC increase, it just breaks even (or even regresses) with the 20-30% clockspeed decrease. TL;DR -- While server chips are pretty much all upside, desktop chips seem to break even or suffer performance regressions.