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>The newer Ryzen 3 and upcoming Alder Lake products are between M1 and M1 Pro sized, and they all have similar total amounts of cache. Increasing the cache siz

>The newer Ryzen 3 and upcoming Alder Lake products are between M1 and M1 Pro sized, and they all have similar total amounts of cache. Increasing the cache sizes to be as large as Apple's phone SOC is an extremely recent decision on AMD and Intel's part, as noted at the M1 introduction. >Last year we had speculated that the A13 had 128KB L1 Instruction cache, Apple has confirmed that it’s actually a massive 192KB instruction cache. That’s absolutely enormous and is 3x larger than the competing Arm designs, and 6x larger than current x86 designs https://www.anandtech.com/show/16226/apple-silicon-m1-a14-deep-dive/2 https://www.anandtech.com/show/16226/apple-silicon-m1-a14-de... > throwing more transistors at the problem doesn't necessarily help power efficiency Getting your performance from IPC improvements at a lower clock (at the cost of die space) instead of pushing the power envelope to hit ever increasing clock speeds seems to be paying off quite well.

hedgehog 5y ago
Ah true, in phone land the differences are extra stark. Given the lower margins and lack of service revenue on the Android side it's not clear if it's economically feasible for Qualcomm etc to match them. It's possible we'll see something similar happen on the Mac side where a something like a M1 Max iMac resets the bar for workstations. Then again maybe not, most laptops still have terrible screens despite Apple showing it's a solvable problem at least five years ago.
- GeekyBear 5y ago
  With Phones, using a wide CPU design that runs at a lower clock has been Apple's strategy for quite some time. For instance, when power leakage became a huge issue at 20nm, Apple was less affected since they ran their clocks so much lower. >Apple is something of the exception here, with the 20nm A8 proving to be a solid SoC, thanks in part to their wide CPU design allowing them to achieve good performance without using high clockspeeds that would exacerbate the problem. https://www.anandtech.com/show/9686/the-apple-iphone-6s-and-iphone-6s-plus-review/2 https://www.anandtech.com/show/9686/the-apple-iphone-6s-and-...

hedgehog 5y ago

Ah true, in phone land the differences are extra stark. Given the lower margins and lack of service revenue on the Android side it's not clear if it's economically feasible for Qualcomm etc to match them. It's possible we'll see something similar happen on the Mac side where a something like a M1 Max iMac resets the bar for workstations. Then again maybe not, most laptops still have terrible screens despite Apple showing it's a solvable problem at least five years ago.

GeekyBear 5y ago
With Phones, using a wide CPU design that runs at a lower clock has been Apple's strategy for quite some time. For instance, when power leakage became a huge issue at 20nm, Apple was less affected since they ran their clocks so much lower. >Apple is something of the exception here, with the 20nm A8 proving to be a solid SoC, thanks in part to their wide CPU design allowing them to achieve good performance without using high clockspeeds that would exacerbate the problem. https://www.anandtech.com/show/9686/the-apple-iphone-6s-and-iphone-6s-plus-review/2 https://www.anandtech.com/show/9686/the-apple-iphone-6s-and-...