3 ms·

Almost all of this is inaccurate. You can read about their silicon program in pretty much any trade magazine for details but for example: their main cores have

Almost all of this is inaccurate. You can read about their silicon program in pretty much any trade magazine for details but for example: their main cores have been in-house designs for about a decade, RAM is on-package not on-die, that is probably only a moderate perf win in itself, they have been contributing to and extending the ISA for many years, etc. What the Apple chips do appear to be is a successful application of the "lead bullets" approach to good engineering. If you compare to Zen 2 it's clear that Apple's designs are not really incomparably better than peers, but they are excellent. With the advantage of better software support and a better manufacturing process than other mobile CPUs they perform really well. They don't directly compete with CPU vendors but hopefully their new products light the fire under their PC counterparts to build better products. I sure hate feeling trapped in their super buggy software ecosystem.

GeekyBear 5y ago
I think one thing that has been fairly unique in the industry is that Apple has been willing to throw silicon die area at a problem. For example, their cache sizes are massive in comparison to anything else in the consumer space. If you sell chips to device manufacturers for a living, increasing die size cuts directly into how much you make per wafer. When you sell devices containing your own custom chips, your profit margin does not depend on the cost of fabbing that chip alone. As a bonus, when everyone else is trying to make a smaller die and cranks up the clocks for performance, you are hugely more power efficient (without giving up performance) when you throw die size at an extra wide instruction decode with a ton of execution units running at a much slower clock speed and have huge reorder buffers so you can track more instructions in flight. https://www.anandtech.com/show/16226/apple-silicon-m1-a14-deep-dive/2 https://www.anandtech.com/show/16226/apple-silicon-m1-a14-de...
- hedgehog 5y ago
  It's an interesting hypothesis, I'm not sure how true this is. The newer Ryzen 3 and upcoming Alder Lake products are between M1 and M1 Pro sized, and they all have similar total amounts of cache. Arguably by using both a bit more area and a more advanced process Apple has a much higher transistor budget to work with, but throwing more transistors at the problem doesn't necessarily help power efficiency. The one area where they have a really decisive advantage is their ability to synchronize OS development with hardware roadmap, then force developers to play along (via app store rules).
  - GeekyBear 5y ago
    >The newer Ryzen 3 and upcoming Alder Lake products are between M1 and M1 Pro sized, and they all have similar total amounts of cache. Increasing the cache sizes to be as large as Apple's phone SOC is an extremely recent decision on AMD and Intel's part, as noted at the M1 introduction. >Last year we had speculated that the A13 had 128KB L1 Instruction cache, Apple has confirmed that it’s actually a massive 192KB instruction cache. That’s absolutely enormous and is 3x larger than the competing Arm designs, and 6x larger than current x86 designs https://www.anandtech.com/show/16226/apple-silicon-m1-a14-deep-dive/2 https://www.anandtech.com/show/16226/apple-silicon-m1-a14-de... > throwing more transistors at the problem doesn't necessarily help power efficiency Getting your performance from IPC improvements at a lower clock (at the cost of die space) instead of pushing the power envelope to hit ever increasing clock speeds seems to be paying off quite well.
    - hedgehog 5y ago
      Ah true, in phone land the differences are extra stark. Given the lower margins and lack of service revenue on the Android side it's not clear if it's economically feasible for Qualcomm etc to match them. It's possible we'll see something similar happen on the Mac side where a something like a M1 Max iMac resets the bar for workstations. Then again maybe not, most laptops still have terrible screens despite Apple showing it's a solvable problem at least five years ago.
      - GeekyBear 5y ago
        With Phones, using a wide CPU design that runs at a lower clock has been Apple's strategy for quite some time. For instance, when power leakage became a huge issue at 20nm, Apple was less affected since they ran their clocks so much lower. >Apple is something of the exception here, with the 20nm A8 proving to be a solid SoC, thanks in part to their wide CPU design allowing them to achieve good performance without using high clockspeeds that would exacerbate the problem. https://www.anandtech.com/show/9686/the-apple-iphone-6s-and-iphone-6s-plus-review/2 https://www.anandtech.com/show/9686/the-apple-iphone-6s-and-...
  - 5y ago

GeekyBear 5y ago

I think one thing that has been fairly unique in the industry is that Apple has been willing to throw silicon die area at a problem. For example, their cache sizes are massive in comparison to anything else in the consumer space. If you sell chips to device manufacturers for a living, increasing die size cuts directly into how much you make per wafer. When you sell devices containing your own custom chips, your profit margin does not depend on the cost of fabbing that chip alone. As a bonus, when everyone else is trying to make a smaller die and cranks up the clocks for performance, you are hugely more power efficient (without giving up performance) when you throw die size at an extra wide instruction decode with a ton of execution units running at a much slower clock speed and have huge reorder buffers so you can track more instructions in flight. https://www.anandtech.com/show/16226/apple-silicon-m1-a14-deep-dive/2 https://www.anandtech.com/show/16226/apple-silicon-m1-a14-de...

hedgehog 5y ago
It's an interesting hypothesis, I'm not sure how true this is. The newer Ryzen 3 and upcoming Alder Lake products are between M1 and M1 Pro sized, and they all have similar total amounts of cache. Arguably by using both a bit more area and a more advanced process Apple has a much higher transistor budget to work with, but throwing more transistors at the problem doesn't necessarily help power efficiency. The one area where they have a really decisive advantage is their ability to synchronize OS development with hardware roadmap, then force developers to play along (via app store rules).
- GeekyBear 5y ago
  >The newer Ryzen 3 and upcoming Alder Lake products are between M1 and M1 Pro sized, and they all have similar total amounts of cache. Increasing the cache sizes to be as large as Apple's phone SOC is an extremely recent decision on AMD and Intel's part, as noted at the M1 introduction. >Last year we had speculated that the A13 had 128KB L1 Instruction cache, Apple has confirmed that it’s actually a massive 192KB instruction cache. That’s absolutely enormous and is 3x larger than the competing Arm designs, and 6x larger than current x86 designs https://www.anandtech.com/show/16226/apple-silicon-m1-a14-deep-dive/2 https://www.anandtech.com/show/16226/apple-silicon-m1-a14-de... > throwing more transistors at the problem doesn't necessarily help power efficiency Getting your performance from IPC improvements at a lower clock (at the cost of die space) instead of pushing the power envelope to hit ever increasing clock speeds seems to be paying off quite well.
  - hedgehog 5y ago
    Ah true, in phone land the differences are extra stark. Given the lower margins and lack of service revenue on the Android side it's not clear if it's economically feasible for Qualcomm etc to match them. It's possible we'll see something similar happen on the Mac side where a something like a M1 Max iMac resets the bar for workstations. Then again maybe not, most laptops still have terrible screens despite Apple showing it's a solvable problem at least five years ago.
    - GeekyBear 5y ago
      With Phones, using a wide CPU design that runs at a lower clock has been Apple's strategy for quite some time. For instance, when power leakage became a huge issue at 20nm, Apple was less affected since they ran their clocks so much lower. >Apple is something of the exception here, with the 20nm A8 proving to be a solid SoC, thanks in part to their wide CPU design allowing them to achieve good performance without using high clockspeeds that would exacerbate the problem. https://www.anandtech.com/show/9686/the-apple-iphone-6s-and-iphone-6s-plus-review/2 https://www.anandtech.com/show/9686/the-apple-iphone-6s-and-...
- 5y ago