4 ms·
> Instead of just the one status register, to be renamed at need the way x86 and ARM do lately, I would append these bits to every register, carried along with
by colejohnson66 5y ago
> Instead of just the one status register, to be renamed at need the way x86 and ARM do lately, I would append these bits to every register, carried along with the value.
Is there any difference? I doubt that Intel and AMD rename the status flags separately. For example, Skylake-X has the same number of physical flags “registers” as physical GPRs.[0]
[0]: https://travisdowns.github.io/blog/2020/05/26/kreg2.html https://travisdowns.github.io/blog/2020/05/26/kreg2.html (the skinny register file next to the GPR ones)
- ncmncm 5y agoIf you need to rename registers, renaming a status register is no more trouble. But having only one way, in the ISA, to mention status is limiting in the same way as having too few named registers.
- colejohnson66 5y agoHow so?
- ncmncm 5y agoIt means that, at the ISA level, only one status can be considered live at any instruction address. If you will need it later, but need to generate another status result, you have to copy the old value somewhere. This is much like in x32, where you had only one visible named AX register, and had to spill its value if you needed it for something else.