4 ms·

I'd really love to find out how much of the m1's performance is due to the advantage of having a custom architecture designed to make Apple's refcounting mania

I'd really love to find out how much of the m1's performance is due to the advantage of having a custom architecture designed to make Apple's refcounting mania actually perform well. I.e. somehow run all their arm code in a way that emulates the M1 instructions on a regular ARM chip with similar clocks, cache etc... probably very hard to do. Maybe you could patch a binary that came out of Apple's compiler to not use the new instructions? The atomics they use to do refcounting definitely have a measurable performance impact on x86.

izacus 5y ago
Nah, most of the performance comes from: - Massive caches - Really really good power efficiency due to good manufacturing node - Massive RAM bandwidth - Very fast I/O performance of the builtin SSD It's a big, expensive chip to manufacture and it pays off with overall performance.
saagarjha 5y ago
There are no "special" M1 refcounting instructions, they're just ARMv8.1 LSE atomics made to go really fast. (You can confirm this pretty easily: objc_retain uses cas.)
- pja 5y ago
  I think that’s the OP’s point? Apple optimised the snot out of their chip for the code they run. Vertical integration works, in other words?
  - MaxikCZ 5y ago
    Sure, vertical integration is nice, but why is it so hard - maybe even impossible, to achieve similar results without it? Windows is such an entrenched ecosystem with millions of PCs running it. The code running on most of them isn't complete blackbox. I find weird that Intel and AMD are not able, despite their cooperation with Microsoft, to achieve similar kinds of results.
    - paulryanrogers 5y ago
      Are there any 5nm CPUs available yet for x86?
      - acdha 5y ago
        This isn’t a recent problem. Sometimes those companies work together but they often are at cross purposes because they each have different incentives whereas at Apple they all report to the same person.
        howinteresting 5y ago
        It's a top-down versus decentralized, market-driven approach, with all the upsides and downsides of each.
    - howinteresting 5y ago
      AMD and Apple aren't playing on a level field currently. We'll see how well the 5nm AMDs with the 3d stacked cache perform when they come out next year.
  - addicted 5y ago
    More likely, being able to use a new architecture that isn’t burdened with decades of legacy compatibility works better than an architecture that is burdened with decades of backward compatibility.
    - acdha 5y ago
      ARM isn’t new and hasn’t been a performance champ for most of the decades it’s been around. The other ARM server implementations tended to be slower but better at perf/watt or perf/dollar — Apple changed that with absolute performance wins as well. That suggests that it’s more the execution by their team than an innate architectural advantage, esophagus given how many other cleaner architectures were wiped out by x86.
  - saagarjha 5y ago
    > somehow run all their arm code in a way that emulates the M1 instructions on a regular ARM chip The comment gave me the impression that the author may believe M1 has some special instructions for reference counting; it does not.
  - fulafel 5y ago
    That's not correct. Architecture generally refers to the ISA and the gp comment referred to special M1 instructions.
- cwizou 5y ago
  Yep, I think it's interesting to note how slow x86 was in general with refcounting even compared to the PowerPC era. It's something that showed early on quite a lot when you compared what was considered light usage at that point in time (say open Word and a couple of Safari tabs), a G4 wasn't ridiculous in those scenarios compared to the first Core 2 machines. While I'm sure the designers paid particular attention to those instructions, it's really x86 being a terrible instruction set than the other way around that create that particular refcounting gap I think.

izacus 5y ago

Nah, most of the performance comes from: - Massive caches - Really really good power efficiency due to good manufacturing node - Massive RAM bandwidth - Very fast I/O performance of the builtin SSD It's a big, expensive chip to manufacture and it pays off with overall performance.

saagarjha 5y ago

There are no "special" M1 refcounting instructions, they're just ARMv8.1 LSE atomics made to go really fast. (You can confirm this pretty easily: objc_retain uses cas.)

pja 5y ago
I think that’s the OP’s point? Apple optimised the snot out of their chip for the code they run. Vertical integration works, in other words?
- MaxikCZ 5y ago
  Sure, vertical integration is nice, but why is it so hard - maybe even impossible, to achieve similar results without it? Windows is such an entrenched ecosystem with millions of PCs running it. The code running on most of them isn't complete blackbox. I find weird that Intel and AMD are not able, despite their cooperation with Microsoft, to achieve similar kinds of results.
  - paulryanrogers 5y ago
    Are there any 5nm CPUs available yet for x86?
    - acdha 5y ago
      This isn’t a recent problem. Sometimes those companies work together but they often are at cross purposes because they each have different incentives whereas at Apple they all report to the same person.
      - howinteresting 5y ago
        It's a top-down versus decentralized, market-driven approach, with all the upsides and downsides of each.
  - howinteresting 5y ago
    AMD and Apple aren't playing on a level field currently. We'll see how well the 5nm AMDs with the 3d stacked cache perform when they come out next year.
- addicted 5y ago
  More likely, being able to use a new architecture that isn’t burdened with decades of legacy compatibility works better than an architecture that is burdened with decades of backward compatibility.
  - acdha 5y ago
    ARM isn’t new and hasn’t been a performance champ for most of the decades it’s been around. The other ARM server implementations tended to be slower but better at perf/watt or perf/dollar — Apple changed that with absolute performance wins as well. That suggests that it’s more the execution by their team than an innate architectural advantage, esophagus given how many other cleaner architectures were wiped out by x86.
- saagarjha 5y ago
  > somehow run all their arm code in a way that emulates the M1 instructions on a regular ARM chip The comment gave me the impression that the author may believe M1 has some special instructions for reference counting; it does not.
- fulafel 5y ago
  That's not correct. Architecture generally refers to the ISA and the gp comment referred to special M1 instructions.
cwizou 5y ago
Yep, I think it's interesting to note how slow x86 was in general with refcounting even compared to the PowerPC era. It's something that showed early on quite a lot when you compared what was considered light usage at that point in time (say open Word and a couple of Safari tabs), a G4 wasn't ridiculous in those scenarios compared to the first Core 2 machines. While I'm sure the designers paid particular attention to those instructions, it's really x86 being a terrible instruction set than the other way around that create that particular refcounting gap I think.