3 ms·
The latest and greatest ARM processor (Cortex-A9) has a penalty for shifting. Their shifts are a bit strange, because any alu op can shift one of the operands.
by mansr 15y ago
The latest and greatest ARM processor (Cortex-A9) has a penalty for shifting. Their shifts are a bit strange, because any alu op can shift one of the operands. For standard alu ops, shifting by an immediate costs one extra cycle, and shifting by a register costs two extra cycles. Mov, i.e, a pure shift, only costs an extra cycle in the register case, but it’s still more expensive than, say, an add.
That is not true whatsoever.
- psykotic 15y agoHow so? The table of cycle timings on ARM's website agrees with what he said: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388g/Chdgjcci.html http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.... On the classic ARM processors like ARM9TDMI, I think post-ALU immediate shifts were free and register shifts were 1 extra cycle.
- mansr 15y agoThat table is vastly simplified. As the document explains, the exact timings cannot be listed in a simple table due to the complexities of out-of-order multi-issue execution. A shifted operand is frequently required to be available as input one cycle earlier than a non-shifted one, simply because the shift happens in an earlier pipeline stage than the main ALU ops, which is presumably what the figure in the table is meant to reflect. If the operand is ready, there is no additional delay. In ARM9 documentation, this behaviour is frequently referred to as the instruction having one or more "early" operands. I verified this just now on an actual A9 using the cycle counter. A sequence of independent adds with shifted inputs executes at two instructions per cycle. If each add is made to depend on the previous, two cycles per instruction are needed as suggested by the table. Short chains of dependent instructions are executed out of order masking the added latency. No ARM processor has ever had a "post-ALU" shift.
- psykotic 15y agoThanks, that makes sense. My ARM knowledge has been either second hand or from book reading, so this is good to know. > No ARM processor has ever had a "post-ALU" shift. Typo. I meant pre-ALU.