4 ms·
L is the latency of the instruction, so 1 clock cycle after the INC r8 instruction another instruction can operate on the result in r8. T is the reciprocal thro
by mkbosmans 5y ago
L is the latency of the instruction, so 1 clock cycle after the INC r8 instruction another instruction can operate on the result in r8.
T is the reciprocal throughput, meaning in this case that the CPU can sustain 2 INC instructions per clock cycle, if there are no data dependencies of course.
In general these numbers will stay the same when counted in clock cycles, regardless of frequency.
- colejohnson66 5y agoTo add: with pipelined processors, it doesn’t make sense to list “clocks per instruction” as a single number. Since the advent of superscalar processors, it makes even less sense. Hence why there’s “latency” and “throughput”.