5 ms·
x86, X64 Instruction Latency, Memory Latency and Cpuid Dumps
- R0b0t1 5y agoWhat about perf counters for these things? Some did exist. My i7-4770K has many not present on newer models, especially in regards to uncore dram control. Did they get removed or are they just not populated in the perf binding for the kernel?
- potiuper 5y agoAny link to the text version of those charts?
- iamcreasy 5y agoCan someone explain how to read the readings from Instruction Latency(InstLatX86). For example how to read the following line, 201 X86 :INC r8 L: 13.36ns= 1.0c T: 6.68ns= 0.50c This instruction is incrementing the value of r8 general purpose register. But I am not sure how to parse L: and T: section. Also, does this number change proportionally if it is in low power mode or if the CPU is undervolted?
- ytch 5y agoThere are some explanation in Comment page: In this dump latency means the time that it takes for the next dependent same-type instruction to start. Throughput means the time that it takes for the next independent same-type instruction to start:
- mkbosmans 5y agoL is the latency of the instruction, so 1 clock cycle after the INC r8 instruction another instruction can operate on the result in r8. T is the reciprocal throughput, meaning in this case that the CPU can sustain 2 INC instructions per clock cycle, if there are no data dependencies of course. In general these numbers will stay the same when counted in clock cycles, regardless of frequency.
- colejohnson66 5y agoTo add: with pipelined processors, it doesn’t make sense to list “clocks per instruction” as a single number. Since the advent of superscalar processors, it makes even less sense. Hence why there’s “latency” and “throughput”.
- rep_lodsb 5y agoWhat's "GenuineIotel"? Did an actual processor report this ID?