This is really fascinating subject and seems like a rich area for research. I was curious about your comment regarding arm and risc-v not having coherent instr

This is really fascinating subject and seems like a rich area for research. I was curious about your comment regarding arm and risc-v not having coherent instruction and data caches. Is this a toggle on these chips hen for turning it on and off? I think I remember reading about some SoC that have this configurable.