4 ms·

Ask HN: Is RISC-V getting any real traction, and if so where?

Blog posts like this one [1] from SiFive are claiming “billions of chips”, but I have no idea what devices those chips are going into, or whether this means there is a decent chance I’m going to be using a RISC-V desktop machine or phone sometime in the near future. Thoughts? [1] https://www.sifive.com/blog/risc-v-is-inevitable

pinewurst 5y ago
I think they’re referring to the odd custom-ish embedded parts, e.g. Western Digital usage in mass produced storage devices that can afford novelty. The problem is that there are really no current commodity embedded RISC-V architecture parts - Chinese dime-a-dozen pseudo-Cortex ripoffs don’t count - remotely comparable in performance/power to better current alternatives. Benchmarks of SiFive’s high end are laughable, being grossly sub-RaspberryPi which is hardly ARM top of the line (and doesn’t claim to be such). As SiFive’s P550 hasn’t materialized beyond PR, one can hardly consider it real. Unless some stealth startup appears with a real Zen/NeoVerse analog, I expect this triumph of hype over reality to continue.
- brucehoult 5y ago
  How would the P550 have "materialised"? It was only announced in June. It takes at least 12-18 months to go from a core being announced to someone incorporating it into an SoC and then manufacture that SoC, let alone have it in products in shops. As is usual in the industry, any serious potential customer will have been able to get the full RTL for the core back in June or July, and evaluate its performance in simulators such as Verilator, or on FPGAs. Claiming it's somehow not "real" is just stupid. There is no serious possibility that a core that boots Linux and runs SPEC etc in an FPGA won't work the same in a properly designed and manufactured SoC. Benchmarks of the HiFive Unmatched are exactly what they should be given its A55-like microarchitecture -- a bit better than a Pi 3 and sometimes close to a Pi 4 on normal compiled C code. It doesn't have SIMD or specialised AES and SHA instructions, so of course benchmarks of that kind of thing are worse than a Pi. If that's important to you then of course don't buy one. RISC-V International last month ratified a number of important extensions including Vector and crypto and those will start appearing in future chips. There are several documented startups working on "M1 class" RISC-V cores, staffed with highly experience highly credible people such as Jim Keller or people who founded PA Semi and then developed ARM cores at Apple (including the M1). There's no magic involved in making a top end RISC-V core, just money and good engineering.
ddingus 5y ago
Embedded. I am not sure it's inevitable at all. That said, it sure looks like ARM did, minus the license fees. RISC-V can enter niche markets where price / performance is necessary on the low end of price and or power. Things are still early though. Extensions are one ambiguity. How many will crop up and what will using them look like? Does one take over the ISA essentially? Math performance, due to no flags and multiple instructions needed where single ones or even just a few less will matter too. Not saying the devices won't perform. They will, just at the cost of code size impacting effective cache size. And no device is really performing today.
- brucehoult 5y ago
  In 64 bit (which is what is important today for mobile and PCs etc), RISC-V has clearly the smallest code size of any ISA, by a considerable margin, with all the benefits of better cache usage you correct note that brings. You don't have to take my word for it -- download the disk images for Fedora or Ubuntu for arm64, amd64, and riscv64 and run the "size" command on your selection of binaries. riscv64 is consistently the smallest, and arm64 the largest.
  - ddingus 5y ago
    I wrote math performance specifically, because that code size is larger and didn't have to be, arguably shouldn't be.
    - znwu 5y ago
      The problem is that, when people say "math", they usually refer to HPC, or sometimes machine learning, or in very rare occasions, symbollic math. They usually don't mean arbitrary-precision math. In fact, I'm not aware of a single serious computation field that must depend on arbitray-precision math. Usually in HPC or ML, if your model overflows, then your model just overflowed. So for those scenarios, I haven't heard of code-size problem argument against RISC-V.
      - ddingus 5y ago

pinewurst 5y ago

I think they’re referring to the odd custom-ish embedded parts, e.g. Western Digital usage in mass produced storage devices that can afford novelty. The problem is that there are really no current commodity embedded RISC-V architecture parts - Chinese dime-a-dozen pseudo-Cortex ripoffs don’t count - remotely comparable in performance/power to better current alternatives. Benchmarks of SiFive’s high end are laughable, being grossly sub-RaspberryPi which is hardly ARM top of the line (and doesn’t claim to be such). As SiFive’s P550 hasn’t materialized beyond PR, one can hardly consider it real. Unless some stealth startup appears with a real Zen/NeoVerse analog, I expect this triumph of hype over reality to continue.

brucehoult 5y ago
How would the P550 have "materialised"? It was only announced in June. It takes at least 12-18 months to go from a core being announced to someone incorporating it into an SoC and then manufacture that SoC, let alone have it in products in shops. As is usual in the industry, any serious potential customer will have been able to get the full RTL for the core back in June or July, and evaluate its performance in simulators such as Verilator, or on FPGAs. Claiming it's somehow not "real" is just stupid. There is no serious possibility that a core that boots Linux and runs SPEC etc in an FPGA won't work the same in a properly designed and manufactured SoC. Benchmarks of the HiFive Unmatched are exactly what they should be given its A55-like microarchitecture -- a bit better than a Pi 3 and sometimes close to a Pi 4 on normal compiled C code. It doesn't have SIMD or specialised AES and SHA instructions, so of course benchmarks of that kind of thing are worse than a Pi. If that's important to you then of course don't buy one. RISC-V International last month ratified a number of important extensions including Vector and crypto and those will start appearing in future chips. There are several documented startups working on "M1 class" RISC-V cores, staffed with highly experience highly credible people such as Jim Keller or people who founded PA Semi and then developed ARM cores at Apple (including the M1). There's no magic involved in making a top end RISC-V core, just money and good engineering.

ddingus 5y ago

Embedded. I am not sure it's inevitable at all. That said, it sure looks like ARM did, minus the license fees. RISC-V can enter niche markets where price / performance is necessary on the low end of price and or power. Things are still early though. Extensions are one ambiguity. How many will crop up and what will using them look like? Does one take over the ISA essentially? Math performance, due to no flags and multiple instructions needed where single ones or even just a few less will matter too. Not saying the devices won't perform. They will, just at the cost of code size impacting effective cache size. And no device is really performing today.

brucehoult 5y ago
In 64 bit (which is what is important today for mobile and PCs etc), RISC-V has clearly the smallest code size of any ISA, by a considerable margin, with all the benefits of better cache usage you correct note that brings. You don't have to take my word for it -- download the disk images for Fedora or Ubuntu for arm64, amd64, and riscv64 and run the "size" command on your selection of binaries. riscv64 is consistently the smallest, and arm64 the largest.
- ddingus 5y ago
  I wrote math performance specifically, because that code size is larger and didn't have to be, arguably shouldn't be.
  - znwu 5y ago
    The problem is that, when people say "math", they usually refer to HPC, or sometimes machine learning, or in very rare occasions, symbollic math. They usually don't mean arbitrary-precision math. In fact, I'm not aware of a single serious computation field that must depend on arbitray-precision math. Usually in HPC or ML, if your model overflows, then your model just overflowed. So for those scenarios, I haven't heard of code-size problem argument against RISC-V.
    - ddingus 5y ago