5 ms·
Are the vector ops variable width? And 1024 bit? The RISC-V standard is quite expansive, I can't tell the intent in the article.
by R0b0t1 5y ago
Are the vector ops variable width? And 1024 bit?
The RISC-V standard is quite expansive, I can't tell the intent in the article.
- znwu 5y agoIt is a 128bit wide vector design. Which means the wdith of actual vector register is 128bit. The 1024bit figure is due to register grouping of up to 8 vector registers which is mandated in the spec.