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StarFive Dubhe 64-bit RISC-V core to be found in 12nm, 2 GHz processors
- R0b0t1 5y agoAre the vector ops variable width? And 1024 bit? The RISC-V standard is quite expansive, I can't tell the intent in the article.
- znwu 5y agoIt is a 128bit wide vector design. Which means the wdith of actual vector register is 128bit. The 1024bit figure is due to register grouping of up to 8 vector registers which is mandated in the spec.
- melony 5y agoWill we see the rise of Libc shims soon like those for JavaScript? RISC V feature support looks notoriously fragmented.
- mhh__ 5y agoMaybe. The technology for "JIT" (i.e. AOT just prior to the program starting) is also relatively mature, so maybe it could go that way. However a lot of these are embedded targets so I don't think we are even close to needing to worry about at least some of these things yet.
- FullyFunctional 5y agoDoes it? It's something I constantly worry about, but so far distributions are holding steady to RV64GC which essentially all 64-bit RISC-V cores support. A few support some proprietary extensions, but those can be ignored by most. The Dubhe core claims to support some of the newly ratified extensions, which if true is great exactly because they are standard and thus doesn't represent fragmentation. I expect of course that libc eventually will start supporting these extensions _where they are present_ but not mandate them.
- marcodiego 5y agoExcept for proprietary extensions, I don't think it will be very different of the x86 world where processors can have a different number of cores, HT, MMX, 3dNow!, SSE(1,2,3,4...), AMX... These extensions didn't destroy x86. I don't think it will be different with RISCV.
- ncmncm 5y agoIt is very, very different. X86 extensions get added onto the sum total of almost all the previous extensions, so that the number of variations to support has grown about linearly with time. RISC-V extensions are more or less all independent, so that the number of variant targets explodes exponentially as they are added to.
- javajosh 5y ago>explodes exponentially Nit pick: it explodes factorially, which is worse than exponential. The superset of a set of N elts is N!. (If order is meaningful (unlikely here), it's slightly worse, which is all permutations of each member of the superset. But that's only ~exponential and is quickly swallowed by the factorial).
- deleted 5y ago[deleted]
- marcodiego 5y agoIt is not different in the sense that my compiler can generate code that runs on RISC-V and runs faster on RISC-V with specific extensions. Binary compatibility, in practice, is not lost.
- ncmncm 5y agoThere is no requirement to execute instructions defined in an extension not supported. So, it means building for RISC-V is necessarily complicated. Worse, if it traps and emulates instructions, then optimizations using extension instructions become radical pessimizations.
- nynx 5y agoMost risc-v cpus stick to the standards, so I'm not worried.
- snvzz 5y agoIf you're building a chip for a server, workstation, laptop, smartphone, then you'll want to adhere to a platform spec profile. RVA22[0] is the first such profile, and among other important things which go a long way to ease cross-vendor software compatibility, it does require RVA22U and RVA22S, which in turn require a set of extensions. [0]: https://github.com/riscv/riscv-platform-specs/blob/main/riscv-platform-spec.adoc https://github.com/riscv/riscv-platform-specs/blob/main/risc...
- jagger27 5y agoGlobalFoundries could be a big player in this market segment. Their lithography tech isn’t bad at all.
- bcrl 5y agoIt has stopped advancing. That's kinda the definition of bad in semiconductors.
- jagger27 5y agoYeah, okay, I know. 12/14 nm on GloFo is still perfectly usable for this class of chip and plenty of other applications. Old != bad.
- happycube 5y ago28nm and 40nm are going to be common for a long long time, too.
- bcrl 5y agoOnly leading edge processes can command a price premium, and for some products (like the high performance CPUs that Intel and AMD make), trailing processes are not economically viable. If a process is not economically viable, I'd consider that to be one possible definition of "bad". In the case of Global Foundries, they lost their anchor customer AMD who now only uses them for an I/O die that will migrate off GloFo's process as soon as their wafer supply agreement permits. That's pretty damned bad and does not bode well for GloFo's continued viability.
- jagger27 5y agoGloFo is booked solid through to 2023[0], and that’s without AMD’s volume. Again, not everything needs to be on leading edge nodes. Since when are trailing edge processes not viable? I have no idea where you’re getting that idea from. For example, in Q1 2021 TSMC made more than 50% of its revenue in processes older than 7nm.[1] Just so you know, TSMC intends to keep ramping up >7nm production for a few more years. There is so much demand for all kinds of nodes that it’s hilarious that you’re still trying to make this argument. 0: https://www.cnbc.com/2021/10/30/globalfoundries-ceo-were-sold-out-of-semiconductor-chip-capacity-through-2023.html https://www.cnbc.com/2021/10/30/globalfoundries-ceo-were-sol... 1: https://www.anandtech.com/show/16621/tsmc-q1-2021-process-node-revenue-more-7nm-no-more-20nm https://www.anandtech.com/show/16621/tsmc-q1-2021-process-no...
- ncmncm 5y agoThis will be the first RISC-V chip I have heard of that implements the popcount instruction. To my knowledge it is not required in any standard profile, so getting a compiler to generate the instruction will be messy. When run on a chip that does not support the instruction, typical 10x optimizations become 10x pessimizations instead.