> Designed for 4 MHz clock speed, ~100-150k instructions/second [1] Given the scale of the breadboarded rat's nest prototype, was this actually achieved? [1]

> Designed for 4 MHz clock speed, ~100-150k instructions/second [1] Given the scale of the breadboarded rat's nest prototype, was this actually achieved? [1] https://github.com/jdah/jdh-8/blob/c621a9980a7d4eb7aa4debc6245827628818aa19/SPEC.txt#L11 https://github.com/jdah/jdh-8/blob/c621a9980a7d4eb7aa4debc62...