> Not to mention it'd be god awful to implement that kind of thing in non programmable level hardware. Not to disagree with you, but to emphasise this - a lot

> Not to mention it'd be god awful to implement that kind of thing in non programmable level hardware. Not to disagree with you, but to emphasise this - a lot of stuff in v6 is intentionally easy to implement in hardware. Stuff like the 64/64 address split, fixed-length headers. The only benefit to fixing head length / next header at 40 bytes is to enable zero-knowledge hardware accel. Essentially similar to people describing one of the benefits to pipelining on the M1 being fixed instruction length - you can pipeline a packet/instruction without parsing it.